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freescale semiconductor document number: mma8652fc data sheet: product preview rev. 0, 08/2012 ? 2 012 freescale semiconductor, inc. all rights reserved. this document contains information on a new product. specifications and information herein are subject to change without notice. xtrinsic mma8652fc 3-axis, 12-bit digital accelerometer the mma8652fc is an intelligent, low-power, three-axis, capacitive micromachined accelerometer with 12 bits of resolution. this accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins. embedded interrupt functions enable overall power savings, by relieving the host processor from continuously polling data. there is access to either low-pass or high-pass filtered data, which minimizes the data analysis required for jolt detection and faster transitions. the device can be configured to generate inertial wake-up interrupt signals from any combination of the configurable embedded functions, enabling the mma8652fc to monitor inertial events and to remain in a low-power mode during periods of inactivity. the mma8652fc is available in a small 10-pin dfn package (2 mm x 2 mm x 1 mm). features ? 1.95v to 3.6v supply voltage ? 1.62v to 3.6v digital interface voltage ? 2g, 4g, and 8g dynamically selectable full-scale ranges ? output data rates (odr) from 1.56 hz to 800 hz ? 12-bit digital output ?i 2 c digital output interface with programmable interrupts ? four embedded channels of configurable motion detection (freefall, motion, pulse, transient) ? orientation (portrait/landscape) detection with programmable hysteresis ? automatic odr change triggered by the auto-wake / sleep state change ? 32-sample fifo ? high-pass filter data available per sample and through the fifo ?self-test typical applications ? ecompass applications tilt compensation ? static orientation detection (portrait/landscape, up/down, left/right, back/front position identification) ? notebook, ereader, and laptop tumble and freefall detection ? real-time orientation detection (virtual reality and gaming 3d user position feedback) ? real-time activity analysis (pedometer step counting, freefall drop detection for hdd, dead-reckoning gps backup) ? motion detection for portable product power saving (auto-sleep and auto-wake for cell phone, pda, gps, gaming) ? shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) ? user interface (menu scrolling by orientation change, tap detection for button replacement ) ordering information part number temperature range package description shipping MMA8652FCR1 -40c to +85c dfn-10 tape and reel mma8652fc top view pin connections vdd scl int1 byp int2 sda gnd gnd vddio gnd 1 2 3 4 5 10 9 8 7 6 mma8652fc 10-pin dfn 2 mm x 2 mm x 1 mm case 2162 top and bottom view
mma8652fc sensors 2 freescale semiconductor, inc. feature comparison of the mma865xfc devices feature list mma8652fc mma8653fc digital resolution (bits) 12 10 digital sensitivity in 2g mode (counts/g) 1024 256 low-power mode yes yes auto-wake yes yes auto-sleep yes yes 32-level fifo yes no low-pass filter yes yes high-pass filter yes no transient detection with high-pass filter yes no orientation detection portrait to landscape = 30, landscape to portrait = 60, and fixed 45 threshold yes yes programmable orientation detection yes no data-ready interrupt yes yes single-tap interrupt yes no double-tap interrupt yes no directional tap interrupt yes no freefall interrupt yes yes motion interrupt with direction yes no
mma8652fc sensors freescale semiconductor, inc. 3 contents 1 block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 orientation definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 recommended application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mechanical and electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 i2c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 zero-g offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 device calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 8-bit or 12-bit data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 internal fifo data buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 low power modes vs. high resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 auto-wake/sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 freefall and motion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7 transient detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.8 tap detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.9 orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.10 interrupt register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.11 serial i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 register quick jump table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 fifo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 system status and id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7 data configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.8 portrait/landscape configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9 freefall/motion configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.10 transient configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.11 pulse configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12 auto-wake/sleep register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.13 system and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.14 data calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7 mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1 overview of soldering considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.2 halogen content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3 pcb mounting/soldering recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8 tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.1 tape dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2 device orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
mma8652fc sensors 4 freescale semiconductor, inc. 1 block diagram and pin descriptions 1.1 block diagram figure 1. block diagram c-to-v converter sda scl i 2 c embedded functions c-to-v internal osc clock gen adc converter vddio gnd x-axis transducer y-axis transducer z-axis transducer 32 data point configurable fifo buffer with watermark freefall and motion detection transient detection (i.e., fast motion, jolt) enhanced orientation with hysteresis and z-lockout single, double auto-wake/auto-sleep configurable with debounce count er and multiple motion interrupts for control auto-wake/sleep active mode sleep vdd & directional tap detection int1 int2 mode options low power low noise + power high resolution normal mode options low power low noise + power high resolution normal active mode wake byp interface mux voltage regulator gain aaf anti-aliasing filter
mma8652fc sensors freescale semiconductor, inc. 5 1.2 pin descriptions figure 2. direction of the detectable accelerations 1.3 orientation definitions figure 3 shows the device configuration in the 6 different orientation modes. there are several registers to configure the orientation detection and are described in detail in the register setting section. figure 3. landscape/portrait orientation direction of the dete ctable accelerations (bottom view) x y z 1 (top view) 1 5 6 10 vdd scl int1 byp int2 sda gnd vddio gnd gnd top view pu earth gravity pin 1 x @ 0g y @ -1g z @ 0g xout @ 1g yout @ 0g zout @ 0g xout @ 0g yout @ 1g zout @ 0g xout @ -1g yout @ 0g zout @ 0g ll pd lr side view front xout @ 0g yout @ 0g zout @ 1g back xout @ 0g yout @ 0g zout @ -1g 652 652 652 652 pu = portrait up lr = landscape right pd = portrait down ll = landscape left
mma8652fc sensors 6 freescale semiconductor, inc. 1.4 recommended application diagram figure 4. application diagram table 1. pin descriptions pin # pin name description notes 1 vdd power supply device power is supplied through the vdd line. power supply decoupling capacitors should be placed as near as possible to the pins 1 and 8 of the device. 2scli 2 c serial clock 7-bit i 2 c device addres s is 0x1d. the control signals scl and sda are not tolerant of voltages more than vddio + 0.3v. if vddio is removed, then the control signals scl and sda will clamp any logic signals with their internal esd protection diodes. the sda and scl i 2 c connections are open drain, and theref ore usually require a pullup resistor. 3 int1 interrupt 1 the interrupt source and pin settings are user-programmable through the i 2 c interface. 4byp internal regulator output capacitor connection 5 int2 interrupt 2 see int1. 6 gnd ground 7 gnd ground 8 vddio digital interface power supply 9 gnd ground 10 sda i 2 c serial data see scl. vdd scl int1 byp int2 sda vddio 1 2 10 9 8 7 6 mma8652fc 0.1 f 1 f 0.1 f 3 4 5 top view vddio vddio 1 k 1 k note: 1 k pullup resistors on int1/int2 are only needed for open-drain. .1 f
mma8652fc sensors freescale semiconductor, inc. 7 2 mechanical and electrical specifications 2.1 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. exposure to maximum rating conditions for extended periods may affect device reliability. table 2. maximum ratings rating symbol value unit maximum acceleration (all axes, 100 s) g max 10,000 g supply voltage vdd -0.3 to + 3.6 v input voltage on any control pin (scl, sda) vin -0.3 to vddio + 0.3 v drop test d drop 1.8 m operating temperature range t op -40 to +85 c storage temperature range t stg -40 to +125 c table 3. esd and latch-up protection characteristics rating symbol value unit human body model hbm 2000 v machine model mm 200 v charge device model cdm 500 v latch-up current at t = 85c ? 100 ma cause the part to otherwise fail. this device is sensitive to mechanical shock. impr oper handling can cause perm anent damage of the part or this part is esd-sensitive. i mproper handling can cause permanent damage to the part.
mma8652fc sensors 8 freescale semiconductor, inc. 2.2 mechanical characteristics table 4. mechanical characteristics at vdd = 2.5v, vddio = 1.8v, t = 25c unless otherwise noted parameter test conditions symbol min typ max unit measurement range fs[1:0] set to 00 2g mode fs 2 g fs[1:0] set to 01 4g mode 4 fs[1:0] set to 10 8g mode 8 sensitivity fs[1:0] set to 00 2g mode so 1024 counts/g fs[1:0] set to 01 4g mode 512 fs[1:0] set to 10 8g mode 256 sensitivity accuracy soa 2.64 % sensitivity change vs. temperature fs[1:0] set to 00 2g mode tcso 0.04 %/c fs[1:0] set to 01 4g mode fs[1:0] set to 10 8g mode zero-g level offset accuracy (1) 1. before board mount. fs[1:0] 2g, 4g, 8g tyoff 40 mg zero-g level offset accuracy post-board mount (2) 2. post-board mount offset specifications ar e based on an 8-layer pcb, relative to 25c. fs[1:0] 2g, 4g, 8g tyoffpbm 60 mg zero-g level change vs. temperature -40c to 85c tcoff 0.3 mg/c self-test output change (3) x y z 3. self-test is one direction only. fs[1:0] set to 0 4g mode vst 50 50 50 lsb odr accuracy 2 mhz clock -20 +20 % output data bandwidth bw odr/3 odr/2 hz output noise normal mode odr = 400 hz noise 216 g/ hz operating temperature range top -40 +85 c package weight tbd g
mma8652fc sensors freescale semiconductor, inc. 9 2.3 electrical characteristics table 5. electrical characteristics at vdd = 2.5v, vddio = 1.8v, t = 25c unless otherwise noted parameter test conditions symbol min typ max unit supply voltage vdd (1) 1. there is no requirement for power s upply sequencing. the vddio input voltage can be higher than the vdd input voltage. 1.95 2.5 3.6 v interface supply voltage vddio (1) 1.62 1.8 3.6 v low power mode odr = 1.56 hz i dd lp 6 a odr = 12.5 hz 6 odr = 50 hz 14 odr = 100 hz 24 odr = 200 hz 44 odr = 400 hz 85 odr = 800 hz 165 normal mode odr = 1.56 hz i dd 24 a odr = 12.5 hz 24 odr = 50 hz 24 odr = 100 hz 44 odr = 200 hz 85 odr = 400 hz 165 odr = 800 hz 165 current during boot sequence, 0.5 msec max duration using recommended bypass cap vdd = 2.5v idd boot 1 ma value of capacitor on byp pin -40c to 85c cap 75 100 470 nf standby mode current at 25c vdd = 2.5v, vddio = 1.8v standby mode i dd stby 1.8 5 a standby mode current over temperature range vdd = 2.5v, vddio = 1.8v standby mode i dd stby tbd tbd a digital high level input voltage scl, sda vih 0.75*vddio v digital low level input voltage scl, sda vil 0.3*vddio v high level output voltage int1, int2 i o = 500 a voh 0.9*vddio v low level output voltage int1, int2 i o = 500 a vol 0.1*vddio v low level output voltage sda i o = 500 a vols 0.1*vddio v output source current voltage high level vout = 0.75 x vdd, vdd = 2.5v i source 3m a output sink current voltage high level vout = 0.25 x vdd, vdd = 2.5v i sink 3m a power-on ramp time tpu 0.001 1000 ms time from vddio on and vdd > vmin until i 2 c is ready for operation cbyp = 100 nf bt 350 500 s turn-on time (standby to first sample available) ton 2/odr + 1 (2) ms turn-on time (power down to first sample available) to n 2/odr + 2 (2) ms
mma8652fc sensors 10 freescale semiconductor, inc. 2.4 i 2 c interface characteristics figure 5. i 2 c slave timing 2. note that the first sample is typically not very precise; on ly the second or third or four th sample (depending on odr/mods se ttings) has full precision. table 6. i 2 c slave timing values (1) 1. all values referred to vih (min) and vil (max) levels. parameter symbol i 2 c fast mode unit min max scl clock frequency f scl 0 400 khz bus free time between stop and start condition t buf 1.3 s (repeated) start hold time t hd;sta 0.6 s (repeated) start setup time t su;sta 0.6 s stop condition setup time t su;sto 0.6 s sda data hold time t hd;dat 0.05 0.9 (2) 2. this device does not stretch the low period (t low ) of the scl signal. s sda valid time (3) 3. t vd;dat = time for data signal from scl low to sda output. t vd;dat 0.9 (2) s sda valid acknowledge time (4) 4. t vd;ack = time for acknowledgement signal from scl low to sd a output (high or low, depending on which one is worse). t vd;ack 0.9 (2) s sda setup time t su;dat 100 ns scl clock low time t low 1.3 s scl clock high time t high 0.6 s sda and scl rise time t r 20 + 0.1 c b (5) 5. c b = total capacitance of one bus line in pf. 300 ns sda and scl fall time t f 20 + 0.1 c b (5) 300 ns pulse width of spikes on sda and scl that must be suppressed by internal input filter t sp 05 0n s handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta
mma8652fc sensors freescale semiconductor, inc. 11 3 terminology 3.1 sensitivity the sensitivity is represented in counts/g. ? in 2g mode, sensitivity = 1024 counts/g. ? in 4g mode, sensitivity = 512 counts/g. ? in 8g mode, sensitivity = 256 counts/g. 3.2 zero-g offset zero-g offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationa ry. a sensor stationary on a horizontal surface will measure 0g in x-axis and 0g in y-axis, whereas the z-axis will measure 1g. the output is ideally in the middle of the dynamic range of the sensor (content of out registers 0x00, data expressed as a 2's complement number). a deviation from ideal value in this case is called zero-g offset. offset is to some extent a result of stress on the mems sensor, and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. 3.3 self-test self-test can be used to verify the transducer and signal chain functionality without the need to apply external mec hanical stimulus. when self-test is activated: ? an electrostatic actuation force is applied to the sensor, simulating a small acceleration. in this case, the sensor outputs w ill exhibit a change in their dc levels which, are related to the selected full scale through the device sensitivity. ? the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
mma8652fc sensors 12 freescale semiconductor, inc. 4 modes of operation figure 6. operating modes for mma8652fc some registers are reset when transitioning from standby to active. these registers are all noted in the device memory map register table. the sleep and wake modes are active modes. for more information about how to use the sleep and wake modes and how to transition between these modes, see section 5, ?functionality? . table 7. operating modes mode i 2 c bus state vdd vddio description off powered down <1.8v vddio can be > vdd ? the device is powered off. ? all analog and digital blocks are shutdown. ?i 2 c bus inhibited. standby i 2 c communication with mma8652fc is possible on vddio = high vdd = high active bit is cleared ? only digital blocks are enabled. ? analog subsystem is disabled. ? internal clocks disabled. active (wake/sleep) i 2 c communication with mma8652fc is possible on vddio = high vdd = high active bit is set all blocks are enabled (digital, analog). sleep wake standby off active
mma8652fc sensors freescale semiconductor, inc. 13 5 functionality the mma8652fc is a low-power, digital output 3-axis linear accelerometer with a i 2 c interface, and has embedded logic that is used to detect events and notify an external microprocessor over interrupt lines. ? 8-bit or 12-bit data, high-pass filtered data, 8-bit or 12-bit configurable 32-sample fifo ? four different oversampling options that allow for the optimum resolution vs. current consumption trade-off to be made for a given application ? low power and auto-wake/sleep modes for reducing current consumption ? single/double tap with directional information (1 channel) ? motion detection with directional information or freefall (1 channel) ? transient/jolt detection based on a high-pass filter, with a settable threshold for detecting the change in acceleration above a threshold with directional information (1 channel) ? flexible user-configurable portrait landscape detection algorithm, for addressing many use cases for screen orientation ? two independent interrupt output pins that are programmable among 7 interrupt sources (data ready, motion/freefall, tap, orientation, transient, fifo and auto-wake) all functionality is available in 2g, 4g or 8g dynamic measurement ranges. there are many configuration settings for enabling a ll of the different functions. separate application notes are available to help configure the device for each embedded functionality. 5.1 device calibration the device is factory calibrated for sensitivity and zero-g offset for each axis. the trim values are stored in non-volatile me mory (nvm). on power-up, the trim parameters are read from nvm and applied to the circuitry. in normal use, further calibration in t he end application is not necessary. however, the mma8652fc allows you to adjust the offset for each axis after power-up, by changing the default offset values. the user offset adjustments are stored in 3 volatile 8-bit r egisters (off_x, off_y, off_z). 5.2 8-bit or 12-bit data the measured acceleration data is stored in the following registers as 2?s complement 12-bit numbers: ? out_x_msb, out_x_lsb ? out_y_msb, out_y_lsb ? out_z_msb, out_z_lsb the most significant 8-bits of each axis are stored in out_x (y , z)_msb, so applications needing only 8-bit results can use these 3 registers (and ignore the out_x/y/z_lsb registers). to do this (use only 8-bit results), the f_read bit in ctrl_reg1 must be set. when the f_read bit is cleared, the fast read mode is disabled. ? when the full-scale is set to 2g , the measurement range is -2g to +1.999g, and each count corresponds to (1/1024)g (0.98mg) at 12-bits resolution. ? when the full-scale is set to 4g , the measurement range is -4g to +3.998g, and each count corresponds to (1/512)g ? (1.96mg) at 12-bits resolution. ? when the full-scale is set to 8g , the measurement range is -8g to +7.996g, and each count corresponds to (1/256)g (3.9 mg) at 12-bits resolution. ? if only the 8-bit results are used , then the resolution is reduced by a factor of 16. for more information about the data manipulation between data formats and modes, see application note an4083, data manipulation and basic settings for xt rinsic mma865xfc accelerometers . there is a device driver available that can be used with the sensor toolbox demo board (lfstbeb865xfc) with this application note. table 8. accelerometer 12-bit output data 12-bit data range 2g (1 mg) range 4g (2 mg) range 8g (4 mg) 0111 1111 1111 1. 999g +3.998g +7.996g 0111 1111 1110 1.998g +3.996g +7.992g ?? ? ? 0000 0000 0001 0.001g +0.002g +0.004g 0000 0000 0000 0.0000g 0.0000g 0.0000g 1111 1111 1111 -0.001g -0.002g -0.004g ?? ? ?
mma8652fc sensors 14 freescale semiconductor, inc. 5.3 internal fifo data buffer mma8652fc contains a 32-sample internal fifo data buffer, which helps minimize traffic across the i 2 c bus. the fifo can also save system power, by allowing the host processor/mcu to go into a sleep mode while the accelerometer independently stores the data (up to 32 samples per axis). the fifo can run at all output data rates. there are options for accessing the full 12-bit data or for accessing only the 8-bit data. when access speed is more important than high resolution, the 8-bit data read is a better option. the fifo contains 4 modes (fill buffer mode, circular buffer mode, trigger mode, and disabled mode), which are described in f_setup register 0x09. ? fill buffer mode collects the first 32 samples and asserts the overflow flag when the buffer is full and another sample arrives. it does not collect any more data until the buffer is read. this benefits data logging applications where all samples must be collected. ? circular buffer mode allows the buffer to be filled and then new data replaces the oldest sample in the buffer. the most recent 32 samples will be stored in the buffer. this benefits situations where the processor is waiting for an specific interrupt to s ignal that the data must be flushed to analyze the event. ? trigger mode will hold the last data up to the point when the trigger occurs, and can be set to keep a selectable number of samples after the event occurs. the mma8652fc fifo buffer has a configurable watermark, allowing the processor to be triggered after a configurable number of samples has filled in the buffer (1 to 32). 5.4 low power modes vs. high resolution modes the mma8652fc can be optimized for lower power modes or for higher resolution of the output data. one of the oversampling schemes of the data can activated when mods = 10 in register 0x2b, which will improve the resolution of the output data only. the highest resolution is achieved at 1.56 hz. there is a trade-off between low power and high resolution. low power can be achieved when the oversampling rate is reduced. when mods = 11, the lowest power is achieved. the lowest power is achieved when the sample rate is set to 1.56 hz. 5.5 auto-wake/sleep mode the mma8652fc can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. the advantage of using the auto-wake/sl eep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed, but spends the majority of the time in the sleep mode (lower current) when the device does not require higher sampling rates. ? auto-wake refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. this may also interrupt the processor to transition from a sleep mode to a higher power mode. 1000 0000 0001 -1.999g -3.998g -7.996g 1000 0000 0000 -2.0000g -4.0000g -8.0000g table 9. accelerometer 8-bit output data 8-bit data range 2g (15.6 mg) range 4g (31.25 mg) range 8g (62.5 mg) 0111 1111 1.9844g +3.9688g +7.9375g 0111 1110 1.9688g +3.9375g +7.8750g ?? ? ? 0000 0001 +0.0156g +0.0313g +0.0625g 0000 0000 0.000g 0.0000g 0.0000g 1111 1111 -0. 0156g -0.0313g -0.0625g ?? ? ? 1000 0001 -1.9844g -3.9688g -7.9375g 1000 0000 -2.0000g -4.0000g -8.0000g table 8. accelerometer 12-bit output data (continued) 12-bit data range 2g (1 mg) range 4g (2 mg) range 8g (4 mg)
mma8652fc sensors freescale semiconductor, inc. 15 ? sleep mode occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period. the device will transition to the specified lower sample rate. it may also alert the processor to go into a lower power mode, t o save on current during this period of inactivity. the interrupts that can wake the device from sleep are the following: tap detection, orientation detection, motion/freefall, and transient detection. the fifo can be configured to hold the data in the buffer until it is flushed, if the fifo gate bit is set (in register 0x2c) and if the fifo cannot wake the device from sleep. the interrupts that can keep the device from falling asleep are the same interrupts that can wake the device?with the addition of the fifo. if the fifo interrupt is enabled and data is being accessed continually servicing the interrupt, then the device will remain in wake mode. 5.6 freefall and motion detection mma8652fc has flexible interrupt architecture for detecting either a freefall or a motion. ? freefall can be enabled where the set threshold must be less than the configured threshold. ? motion can be enabled where the set threshold must be greater than the configured threshold. the motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset); the freefall configuration does not use the high-pass filter. 5.6.1 freefall detection the detection of ?freefall? involves the monitoring of the x, y , and z axes for the condition where the acceleration magnitude is below a user-specified threshold for a user-definable amount of time . the usable threshold ranges are normally between 100 mg and 500 mg. 5.6.2 motion detection motion is often used to simply alert the main processor that the device is currently in use. when the acceleration exceeds a se t threshold, the motion interrupt is asserted. a motion can be a fast moving shake or a slow moving tilt. this will depend on the threshold and timing values configured for the event. ? the motion detection function can analyze static acceleration changes or faster jolts. for example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2g. this condition would need to occur for a minimum of 100 ms to ensure that the event was not just noise. the timing value is set by a configurable debounce counter. the debounce counter acts like a filter to determine whether the condition exists for configurable set of time (like 100 ms or longer). ? to detect the direction of the motion, there is also directional data available in the source register. this is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections. 5.7 transient detection the mma8652fc has a built-in high pass filter. acceleration data goes through the high pass filter, eliminating the offset (dc) and low frequencies. the high pass filter cutoff frequency can be set to 4 different frequencies, which depends on the output d ata rate (odr). a higher cutoff frequency ensures that the dc data (or slower moving data) will be filtered out, allowing only the higher frequencies to pass. the embedded transient detection function uses the high-pass filtered data, allowing you to set the threshold and debounce counter. the transient detection feature can be used in the same manner as the motion detection feature, by bypassing the high-pass filter. there is an option in the configuration register to do this, which adds more flexib ility to accommodate various use cases. many applications use the accelerometer?s static acceleration readings (like tilt), which measure the change in acceleration due to gravity only. these functions benefit from acceleration data being filtered with a low-pass filter where high frequency data is considered noise. however, there are many functions where the accelerometer must analyze dynamic acceleration . functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. it is simpler to inter pret these functions (which are dependent on dynamic acceleration data) when the static component has been removed. the transient detection function can be routed to either interrupt pin through bit 5 in ctrl_reg5 register (0x2e). registers 0x1d ? 0x20 are the dedicated transient detection configuration registers. the source register contains directional data to determine the direction of the acceleration (either positive or negative). 5.8 tap detection the mma8652fc has embedded single/double and directional tap detection.
mma8652fc sensors 16 freescale semiconductor, inc. ? the tap detection function has various customizing timers, for setting the pulse time width and the latency time between pulses. there are programmable thresholds for all three axes. ? the tap detection can be configured to run through the high-pass filter and also through a low-pass filter, which provides more customizing and tunable tap detection schemes. ? the status register provides updates on the axes where the event was detected and the direction of the tap. 5.9 orientation detection the mma8652fc incorporates an advanced algorithm for orientation detection (ability to detect all 6 orientations) with configurable trip points. the embedded algorithm allows the selection of the mid-point with the desired hysteresis value. the mma8652fc orientation detection algorithm confirms the reliability of the function with a configurable z-lockout angle. based on the known functionality of linear accelerometers, it is not possible to rotate the device about the z-axis, to detect change in acceleration at slow angular speeds. the angle at which the device no longer detects the orientation change is referred to a s the ?z-lockout angle?. the device operates down to 14 from the flat position. figure 8 and figure 9 show the definitions of the trip angles, going from landscape to portrait and then from portrait to landscape. figure 7. landscape/portrait orientation figure 8. landscape to portrait transition top view pu earth gravity pin 1 x @ 0g y @ -1g z @ 0g xout @ 1g yout @ 0g zout @ 0g xout @ 0g yout @ 1g zout @ 0g xout @ -1g yout @ 0g zout @ 0g ll pd lr side view front xout @ 0g yout @ 0g zout @ 1g back xout @ 0g yout @ 0g zout @ -1g 652 652 652 652 portrait landscape to portrait 90 trip angle = 60 0 landscape portrait portrait to landscape 90 trip angle = 30 0 landscape
mma8652fc sensors freescale semiconductor, inc. 17 . figure 9. z-tilt angle lockout transition 5.10 interrupt regist er configurations there are 7 configurable interrupts in the mma8652fc: data ready, motion/freefall, tap (pulse), orientation, transient, fifo events, and auto-sleep events. figure 10. system interrupt generation ? the mma8652fc features an interrupt signal that indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. ? the mma8652fc may also be configured to generate other interrupt signals accordingly, to the programmable embedded functions of the device for motion, freefall, transient, orientation, and tap. 5.11 serial i 2 c interface acceleration data may be accessed through an i 2 c interface, thus making the device particularly suitable for direct interfacing to a microcontroller. the acceleration data and configuration registers embedded inside the mma8652fc are accessed through the i 2 c serial interface ( table 10 ). ? to enable the i 2 c interface, vddio line must be tied high (i.e., to the interface supply voltage). if vdd is not present and vddio is present, then the mma8652fc is in off mode?and communications on the i 2 c interface are ignored. upright normal 90 z-lock = 29 0 flat detection region lockout region figure 9 shows the z-angle lockout region. when lifting the device upright from the flat position, the device will be active for orientation detection as low as 14 from 0 flat. this is user-configurable. the default angle is 29, but the angle can be set as low as 14. interrupt controller data ready motion/freefall tap (pulse) orientation transient fifo auto-sleep int enable int cfg int1 int2 77 7 configurable interrupts these 7 interrupt sources can be routed to one of two interrupt pins. the interrupt source must be enabled and configured. if the event flag is asserted because the event condition is detected, then the corresponding interrupt pin (int1 or int2) will assert.
mma8652fc sensors 18 freescale semiconductor, inc. ?the i 2 c interface may be used for communications between other i 2 c devices; the mma8652fc does not affect the i 2 c bus. the i 2 c interface is compliant with fast mode (400 khz), and normal mode (100 khz) i 2 c standards ( table 6 ). i 2 c operation: 1. the transaction on the bus is started through a start condition (start) signal. a start condition is defined as a high-to- low transition on the data line while the scl line is held high. after start has been transmitted by the master, the bus is considered busy. 2. the next byte of data transmitted after start contains the slave address in the first 7 bits, and the 8th bit tells whether the master is receiving data from the slave or is transmitting data to the slave . 3. after a start condition and when an address is sent, each device in the system compares the first 7 bits with its address. if the device?s address matches the sent address, then the device considers itself addressed by the master. 4. the 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ack). the transmitter must release the sda line during the ack period. the receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock period. 5. a master may also issue a repeated start during a data transfer. the mma8652fc expects repeated starts to be used to randomly read from specific registers. 6. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition (stop). a data transfer is always terminated by a stop . the mma8652fc's standard slave address is 0011101 or 0x01d. the slave addresses are factory programmed; alternate addresses are available upon request. 5.11.1 single byte read 1. the transmission of an 8-bit command begins on the falling edge of scl. after the 8 clock cycles are used to send the command, note that the data returned is sent with the msb first after the data is received. figure 11 shows the timing diagram for the accelerometer 8-bit i 2 c read operation. 2. the master (or mcu) transmits a start condition (st) to the mma8652fc [slave address (0x1d), with the r/w bit set to ?0? for a write], and the mma8652fc sends an acknowledgement. 3. next the master (or mcu) transmits the address of the register to read, and the mma8652fc sends an acknowledgement. 4. the master (or mcu) transmits a repeated start condition (sr) and then addresses the mma8652fc (0x1d), with the r/ w bit set to ?1? for a read from the previously selected register. 5. the slave then acknowledges and transmits the data from the requested register. the master does not acknowledge (nak) the transmitted data, but transmits a stop condition to end the data transfer. figure 11. single byte read timing (i 2 c) table 10. serial interface pins pin name pin description notes scl i 2 c serial clock there are two signals associated with the i 2 c bus; the serial clock line (scl) and the serial data line (sda). ? sda is a bidirectional line used for sending and receiving the data to/from the interface. ? external pullup resistors connected to vddio are expected for sda and scl. when the bus is free, both scl and sda lines are high. sda i 2 c serial data table 11. i 2 c device address sequence command [6:0] device address [6:0] device address r/w 8-bit final value read 0011101 0x1d 1 0x3b write 0011101 0x1d 0 0x3a master st device address[7:1] w register address[7:0] sr device address[7:1] r nak sp slave ak ak ak data[7:0]
mma8652fc sensors freescale semiconductor, inc. 19 for the following subsections, use the following legend. 5.11.2 multiple byte read (see table 11 for next auto-increment address.) 1. when performing a multi-byte read or ?burst read?, the mma8652fc automatically increments the received register address commands after a read command is received. 2. after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each mma8652fc acknowledgment (ak) is received, 3. until a no acknowledge (nak) occurs from the master, 4. followed by a stop condition (sp), which signals the end of transmission. figure 12. multiple byte read timing (i 2 c) 5.11.3 single byte write 1. to start a write command, the master transmits a start condition (st) to the mma8652fc, slave address ($1d) with the r/w bit set to ?0? for a write, 2. the mma8652fc sends an acknowledgement. 3. next the master (mcu) transmits the address of the register to write to, and the mma8652fc sends an acknowledgement. 4. then the master (or mcu) transmits the 8-bit data to write to the designated register, and the mma8652fc sends an acknowledgement that it has received the data. because this transmission is complete, the master transmits a stop condition (sp) to the data transfer. the data sent to the mma8652fc is now stored in the appropriate register. figure 13. single byte write timing (i 2 c) 5.11.4 multiple byte write (see table 11 for next auto-increment address.) 1. after a write command is received, the mma8652fc automatically increments the received register address commands. 2. therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each mma8652fc acknowledgment (ack) is received. legend st: start condition sp: stop condit ion nak: no acknowledge w: write = 0 sr: repeated start condition ak: acknowledge r: read = 1 master st device address[7:1] w register address[7:0] sr device address[7:1] r ak slave ak ak ak data[7:0] master ak ak nak sp slave data[7:0] data[7:0] data[7:0] master st device address[7:1] w register address[7:0] data[7:0] sp slave ak ak ak
mma8652fc sensors 20 freescale semiconductor, inc. figure 14. multiple byte write timing (i 2 c) master st device address[7:1] w register address[7:0] data[7:0] data[7:0] sp slave ak ak ak ak
mma8652fc sensors freescale semiconductor, inc. 21 6 register descriptions 6.1 register quick jump table 6.2 register address map click the blue register name to go to the register description. data 0x00: status data status register (f_mode = 00) 0x01: out_x_msb, accelerometer x-axis data register 0x02: out_x_lsb, accelerometer x-axis data register 0x03: out_y_msb, accelerometer y-axis data register 0x04: out_y_lsb, accelerometer y-axis data register 0x05: out_z_msb, accelerometer z-axis data register 0x06: out_z_lsb, accelerometer z-axis data register fifo 0x00: f_status fifo status register (f_mode > 0) 0x09: f_setup fifo setup register system status and id 0x0a: trig_cfg trigger configuration register 0x0b: sysmod system mode register 0x0c: int_source system interrupt status register 0x0d: who_am_i device id register data configuration 0x0e: xyz_data_cfg register 0x0f: hp_filter_cutoff high-pass filter register portrait/landscape configuration and status 0x10: pl_status portrait/landscape status register 0x11 portrait/landscape configuration register 0x12 portrait/landscape debounce register 0x13: pl_bf_zcomp back/front and z compensation register 0x14: p_l_ths_reg portrait/landscape threshold and hysteresis register freefall/motion configuration and status 0x15: ff_mt_cfg freefall/motion configuration register 0x16: ff_mt_src freefall/motion source register 0x17: ff_mt_ths freefall and motion threshold register 0x18 ff_mt_count debounce register transient configuration and status 0x1d: transient_cfg register 0x1e transient_src register 0x1f transient_ths register 0x20 transient_count register pulse configuration and status 0x21: pulse_cfg pulse configuration register 0x22: pulse_src pulse source register 0x23 ? 0x25: pulse_thsx, y, z pulse threshold for x, y and z registers 0x26: pulse_tmlt pulse time window 1 register 0x27: pulse_ltcy pulse latency timer register 0x28 pulse_wind register (read/write) auto-wake/sleep 0x29: aslp_count, auto-wake/sleep detection register (read/write) system control 0x2a: ctrl_reg1 system control 1 register 0x2b: ctrl_reg2 system control 2 register 0x2c: ctrl_reg3 interrupt control register 0x2d: ctrl_reg4 interrupt enable register (read/write) 0x2e ctrl_reg5 interrupt configuration register (read/write) data calibration 0x2f: off_x offset correction x register 0x30: off_y offset correction y register 0x31: off_z offset correction z register table 12. register address map name type register address auto-increment address default hex value comment fmode = 0 f_read = 0 fmode > 0 f_read = 0 fmode = 0 f_read = 1 fmode > 0 f_read = 1 status/ f_status ((1))((2)) r 0x00 0x01 00000000 0x00 fmode = 0, real time status fmode > 0, fifo status out_x_msb (1)(2) r 0x01 0x02 0x01 0x03 0x01 output ? [7:0] are 8 msbs of 12-bit sample. root pointer to xyz fifo data. out_x_lsb (1)(2) r 0x02 0x03 0x00 output ? [7:4] are 4 lsbs of 12-bit real-time sample out_y_msb (1)(2) r 0x03 0x04 0x05 0x00 output ? [7:0] are 8 msbs of 12-bit real-time sample out_y_lsb (1)(2) r 0x04 0x05 0x00 output ? [7:4] are 4 lsbs of 12-bit real-time sample
mma8652fc sensors 22 freescale semiconductor, inc. out_z_msb (1)(2) r 0x05 0x06 0x00 output ? [7:0] are 8 msbs of 12-bit real-time sample out_z_lsb (1)(2) r 0x06 0x00 output ? [7:4] are 4 lsbs of 12-bit real-time sample reserved r 0x07 0x08 ? ? ? ? ? ? reserved. read return 0x00. f_setup (1)((3)) r/w 0x09 0x0a 00000000 0x00 fifo setup trig_cfg (1)(4) r/w 0x0a 0x0b 00000000 0x00 map of fifo data capture events sysmod (1)(2) r 0x0b 0x0c 00000000 0x00 current system mode int_source (1)(2) r 0x0c 0x0d 00000000 0x00 interrupt status who_am_i (1) r 0x0d 0x0e 01001010 0x4a device id (0x4a) xyz_data_cfg (1)((4)) r/w 0x0e 0x0f 00000000 0x00 dynamic range settings hp_filter_cutoff (1)(4) r/w 0x0f 0x10 00000000 0x00 high-pass filter selection pl_status (1)(2) r 0x10 0x11 00000000 0x00 landscape/portrait orientation status pl_cfg (1)(4) r/w 0x11 0x12 10000000 0x80 landscape/portrait configuration. pl_count (1)(3) r/w 0x12 0x13 00000000 0x00 landscape/portrait debounce counter pl_bf_zcomp (1)(4) r/w 0x13 0x14 01000100 0x44 back/front, z-lock trip threshold p_l_ths_reg (1)(4) r/w 0x14 0x15 10000100 0x84 portrait/landscape threshold and hysteresis ff_mt_cfg (1)(4) r/w 0x15 0x16 00000000 0x00 freefall/motion functional block configuration ff_mt_src (1)(2) r 0x16 0x17 00000000 0x00 freefall/motion event source register ff_mt_ths (1)(3) r/w 0x17 0x18 00000000 0x00 freefall/motion threshold register ff_mt_count (1)(3) r/w 0x18 0x19 00000000 0x00 freefall/motion debounce counter reserved r 0x19 0x1a 0x1b 0x1c ? ? ? ? ? ? reserved. read return 0x00. transient_cfg (1)(4) r/w 0x1d 0x1e 00000000 0x00 transient functional block configuration transient_src (1)(2) r 0x1e 0x1f 00000000 0x00 transient event status register transient_ths (1)(3) r/w 0x1f 0x20 00000000 0x00 transient event threshold transient_count (1)(3) r/w 0x20 0x21 00000000 0x00 transient debounce counter pulse_cfg (1)(4) r/w 0x21 0x22 00000000 0x00 pulse enable configuration pulse_src (1)(2) r 0x22 0x23 00000000 0x00 pulse detection source pulse_thsx (1)(3) r/w 0x23 0x24 00000000 0x00 x pulse threshold pulse_thsy (1)(3) r/w 0x24 0x25 00000000 0x00 y pulse threshold pulse_thsz (1)(3) r/w 0x25 0x26 00000000 0x00 z pulse threshold pulse_tmlt (1)(4) r/w 0x26 0x27 00000000 0x00 time limit for pulse pulse_ltcy (1)(4) r/w 0x27 0x28 00000000 0x00 latency time for 2 nd pulse table 12. register address map (continued) name type register address auto-increment address default hex value comment fmode = 0 f_read = 0 fmode > 0 f_read = 0 fmode = 0 f_read = 1 fmode > 0 f_read = 1
mma8652fc sensors freescale semiconductor, inc. 23 note auto-increment addresses that are not a simple increment are highlighted in bold . the auto-increment addressing is only enabled when device registers are read using i 2 c burst read mode . the internally stored auto-increment address is cleared whenever an i 2 c stop condition is detected. pulse_wind (1)(4) r/w 0x28 0x29 00000000 0x00 window time for 2nd pulse aslp_count (1)(4) r/w 0x29 0x2a 00000000 0x00 counter setting for auto-sleep ctrl_reg1 (1)(4) r/w 0x2a 0x2b 00000000 0x00 data rates and modes setting ctrl_reg2 (1)(4) r/w 0x2b 0x2c 00000000 0x00 sleep enable, os modes, rst, st ctrl_reg3 (1)(4) r/w 0x2c 0x2d 00000000 0x00 wake from sleep, ipol, pp_od ctrl_reg4 (1)(4) r/w 0x2d 0x2e 00000000 0x00 interrupt enable register ctrl_reg5 (1)(4) r/w 0x2e 0x2f 00000000 0x00 interrupt pin (int1/int2) map off_x (1)(4) r/w 0x2f 0x30 00000000 0x00 x-axis offset adjust off_y (1)(4) r/w 0x30 0x31 00000000 0x00 y-axis offset adjust off_z (1)(4) r/w 0x31 0x0d 00000000 0x00 z-axis offset adjust 1. register contents are preserved when a transi tion from active to standby mode occurs. 2. register contents are reset when a transit ion from standby to active mode occurs. 3. register contents can be modified at any ti me in either standby or active mode. a write to this register will cause a reset of the corresponding internal system debounce counter. 4. register contents can only be modified while the device is in st andby mode; the only exceptions to this are the ctrl_reg1[act ive] and ctrl_reg2[rst] bits. table 12. register address map (continued) name type register address auto-increment address default hex value comment fmode = 0 f_read = 0 fmode > 0 f_read = 0 fmode = 0 f_read = 1 fmode > 0 f_read = 1
mma8652fc sensors 24 freescale semiconductor, inc. 6.3 register summary table 13. mma8652fc register summary reg name definition type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 status/f_status data status r r zyxow zow yow xow zyxdr zdr ydr xdr 01 out_x_msb 12-bit x data r r xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 02 out_x_lsb 12-bit x data r r xd3 xd2 xd1 xd0 0 0 0 0 03 out_y_msb 12-bit y data r r yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 04 out_y_lsb 12-bit y data r r yd3 yd2 yd1 yd0 0 0 0 05 out_z_msb 12-bit z data r r zd11 zd10 zd9 zd8 zd7 zd6 zd5 zd4 06 out_z_lsb 12-bit z data r r zd3 zd2 zd1 zd0 0 0 0 0 09 f_setup fifo setup r/w r/w f_mode1 f_mode0 f_wmrk5 f_wmrk4 f_wmrk3 f_wmrk2 f_wmrk1 f_wmrk0 0a trig_cfg fifo triggers r/w r/w ? ? trig_trans trig_lndprt trig_pulse trig_ff_mt ? ? 0b sysmod system mode r r fgerr fgt_4 fgt_3 fgt_2 fgt_1 fgt_0 sysmod1 sysmod0 0c int_source interrupt status r r src_aslp src_fi fo src_trans src_lndprt src_pulse src_ff_mt ? src_drdy 0d who_am_i id register r r 0 1 0 0 1 0 1 0 0e xyz_data_cfg data config r/w r/w ? ? ? hpf_out ? ? fs1 fs0 0f hp_filter_cutoff hp filter setting r/w r/w ? ? pulse_hpf_byp pulse_lpf_en ? ? sel1 sel0 10 pl_status pl status r r newlp lo ? ? ? lapo[1] lapo[0] bafro 11 pl_cfg pl configuration r/w r/w dbcntm pl_en ? ? ? ? ? ? 12 pl_count pl debounce r/w r/w dbnce[7] dbnce[6] db nce[5] dbnce[4] dbnce[3] dbnce[2] dbnce[1] dbnce[0] 13 pl_bf_zcomp pl back/front z comp r/w r/w bkfr[1] bkfr[0] ? ? ? zlock[2] zlock[1] zlock[0] 14 p_l_ths_reg pl threshold r/w r/w p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] hys[2] hys[1] hys[0] 15 ff_mt_cfg freefall/motion config r/w r/w ele oae zefe yefe xefe ? ? ? 16 ff_mt_src freefall/motion source r r ea ? zhe zhp yhe yhp xhe xhp 17 ff_mt_ths freefall/motion threshold r/w r/w dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 18 ff_mt_count freefall/motion debounce r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 1d transient_cfg transient config r/w r/w ? ? ? ele ztefe ytefe xtefe hpf_byp 1e transient_src transient source r r ? ea ztranse z_trans_pol ytranse y_trans_pol xtranse x_trans_pol 1f transient_ths transient threshold r/w r/w dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 20 transient_count transient debounce r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 21 pulse_cfg pulse config r/w r/w dpa ele zdpefe zspefe ydpefe yspefe xdpefe xspefe 22 pulse_src pulse source r r ea axz axy axx dpe pol_z pol_y pol_x 23 pulse_thsx pulse x threshold r/w r/w ? thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 24 pulse_thsy pulse y threshold r/w r/w ? thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 25 pulse_thsz pulse z threshold r/w r/w ? thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 26 pulse_tmlt pulse first timer r/w r/w tmlt7 tmlt6 tmlt5 tmlt4 tmlt3 tmlt2 tmlt1 tmlt0 27 pulse_ltcy pulse latency r/w r/w ltcy7 ltcy6 ltcy5 ltcy4 ltcy3 ltcy2 ltcy1 ltcy0 28 pulse_wind pulse 2nd window r/w r/w wind7 wind6 wind5 wi nd4 wind3 wind2 wind1 wind0 29 aslp_count auto-sleep counter r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 2a ctrl_reg1 control reg1 r/w r/w aslp_rate1 aslp_rate0 dr2 dr1 dr0 ? f_read active 2b ctrl_reg2 control reg2 r/w r/w st rst ? smods1 smods0 slpe mods1 mods0
mma8652fc sensors freescale semiconductor, inc. 25 2c ctrl_reg3 control reg3 (wake interrupts from sleep) r/w r/w fifo_gate wake_trans wake_lndprt wake_pulse wake_ff_mt ? ipol pp_od 2d ctrl_reg4 control reg4 (interrupt enable map) r/w r/w int_en_aslp int_en_fifo int_en_trans int_en_lndprt int_en_pulse int_en_ff_mt ? int_en_drd y 2e ctrl_reg5 control reg5 (interrupt configuration) r/w r/w int_cfg_aslp int_cfg_fifo int_cfg_trans int_cfg_lndpr t int_cfg_puls e int_cfg_ff_mt ? int_cfg_dr dy 2f off_x x-axis 0g offset r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 30 off_y y-axis 0g offset r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 31 off_z z-axis 0g offset r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 table 13. mma8652fc register summary (continued) reg name definition type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mma8652fc sensors 26 freescale semiconductor, inc. 6.4 data registers the following are the data registers for the mma8652fc device. for more information about data manipulation in the mma8652fc, see application note an4083, data manipulation and basic settings for xtrinsic mma865xfc accelerometers. ? when the f_mode bits (f_setup register 0x09, bit 6 and 7) are cleared, the fifo is not on. register 0x00 reflects the real-time status information of the x, y and z sample data. ? when the f_mode value is greater than zero, then the fifo is on (in either fill, circular, or trigger mode). in this case, register 0x00 will reflect the status of the fifo. it is expected that when the fifo is on, the user will access the data from register 0x01 (x_msb) for either the 12-bit or 8-bit data. ? when accessing the 8-bit data, the f_read bit (register 0x2a) is set, which modifies the auto-incrementing to skip over the lsb data. ? when the f_read bit is cleared, the 12-bit data is read, accessing all 6 bytes sequentially (x_msb, x_lsb, y_msb, y_lsb, z_msb, z_lsb). 6.4.1 0x00: status data status register (f_mode = 00) when f_mode = 0, register 0x00 reflects the real-time status information of the x, y and z sample data; it contains the x, y, a nd z data overwrite and data ready flag. register quick jump table b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 zyxow zow yow xow zyxdr zdr ydr xdr figure 15. f_mode = 00: 0x00 status: data status register (read-only) table 14. status register bits bit(s) field description notes 7zyxow x, y, z-axis data overwrite ? set whenever a new acceleration data is produced before completing the retrieval of the previous set . this event occurs when the content of at least one acceleration data register (i.e., out_x, out_y, out_z) has been overwritten. ? cleared when the high bytes of the acceleration data (out_x_msb, out_y_msb, out_z_msb) of all the channels are read. 0 no data overwrite has occurred (default) 1 previous x, y, or z data was overwritten by new x, y, or z data before it (the previous x, y, or z data) was read 6zow z-axis data overwrite for # = z, y, or x: ? set whenever a new acceleration sample related to the #-axis is generated before the retrieval of the previous sample . when this occurs, the previous sample is overwritten. ? cleared whenever the out_ # _msb register is read. 0 no data overwrite has occurred (default) 1 previous z-axis data was overwritten by new # -axis data before it (the previous # -axis data) was read 5yow y-axis data overwrite 4xow x-axis data overwrite 3zyxdr x, y, z-axis new data ready ? set when a new sample for any of the enabled channels is available. ? cleared when the high-bytes of the acceleration data (out_x_msb, out_y_msb, out_z_msb) of all the channels are read. 0 no new set of data ready (default) 1 a new set of data is ready 2zdr z-axis new data available for # = z, y, or x ? set whenever a new acceleration sample related to the #-axis is generated. ? cleared whenever the out_ # _msb register is read. 0 no new # -axis data ready (default) 1new # -axis data is ready 1ydr y-axis new data available 0xdr x-axis new data available
mma8652fc sensors freescale semiconductor, inc. 27 6.4.2 0x01: out_x_msb, accelerometer x-axis data register 6.4.3 0x02: out_x_lsb, accelerometer x-axis data register 6.4.4 0x03: out_y_msb, accelerometer y-axis data register 6.4.5 0x04: out_y_lsb, accelerometer y-axis data register 6.4.6 0x05: out_z_msb, accelerometer z-axis data register 6.4.7 0x06: out_z_lsb, accelerometer z-axis data register these registers contain the x-axis, y-axis, and z-axis12-bit output sample data (expressed as 2's complement numbers). note: ? if the fifo data output register driver is disabled , then the sample data output registers store the current sample data. ? if the fifo data output register driver is enabled (f_mode > 00), then the sample data output registers point to the head of the fifo buffer (register 0x01 x_msb), which contains the previous 32 x, y, and z data samples. register quick jump table register quick jump table register quick jump table register quick jump table register quick jump table register quick jump table ? out_x_msb, out_x_lsb, out_y_msb, out_y_lsb, out_z_msb, and out_z_lsb are stored in the auto- incrementing address range of 0x01 ? 0x06, to reduce reading the status followed by 12-bit axis data to 7 bytes. if the f_read bit is set (0x2a bit 1), then auto-increment will skip over lsb registers (to access the msb data only). this will shorten the data acquisition from 7 bytes to 4 bytes. ? the lsb registers can only be read immediately following the read access of the corresponding msb register. ? a random read access to the lsb registers is not possible. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 figure 16. 0x01 out_x_msb: x_msb register (read-only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd3 xd2 xd1 xd0 0 0 0 0 figure 17. 0x02 out_x_lsb: x_lsb register (read-only) b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 figure 18. 0x03 out_y_msb: y_msb register (read-only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yd3 yd2 yd1 yd0 0 0 0 0 figure 19. 0x04 out_y_lsb: y_lsb register (read-only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zd11 zd10 zd9 zd8 zd7 zd6 zd5 zd4 figure 20. 0x05 out_z_msb: z_msb register (read-only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zd3 zd2 zd1 zd0 0 0 0 0 figure 21. 0x06 out_z_lsb: z_lsb register (read-only)
mma8652fc sensors 28 freescale semiconductor, inc. ? reading the msb register and then the lsb register in sequence ensures that both bytes (lsb and msb) belong to the same data sample, even if a new data sample arrives between reading the msb and the lsb byte. ? if the fifo is enabled (f_mode > 00), then register 0x01 points to the fifo read pointer, while registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read.
mma8652fc sensors freescale semiconductor, inc. 29 6.5 fifo registers the following registers are used to configure the fifo. for more information about the fifo, see application note an4083, data manipulation and basic settings for xtrinsic mma865xfc accelerometers. 6.5.1 0x00: f_status fifo status register (f_mode > 0) when f_mode > 0, register 0x00 becomes the fifo status register, which is used to retrieve information about the fifo. the fifo status register has a flag for the overflow and watermark, and also has a counter (which can be read to obtain the number of samples stored in the buffer when the fifo is enabled). register quick jump table the f_ovf and f_wmrk_flag flags remain asserted while the event source is still active, but you can clear the fifo interrupt bit flag in the interrupt source register (int_source) by reading the f_status register. in this case, the src_fifo bit in the int_source register will be set again when the next data sample enters the fifo. therefore, the f_ovf bit flag will remain asserted while the fifo has overflowed and the f_wmrk_flag bit flag will remain asserted while the f_cnt value is equal to or greater than then f_wmrk value. ? if the fifo overflow flag is cleared and f_mode = 11, then the fifo overflow flag will remain 0 before the trigger event (even if the fifo is full and overflows). ? if the fifo overflow flag is set and f_mode is = 11, then the fifo has stopped accepting samples. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f_ovf f_wmrk_flag f_cnt5 f_cnt4 f_cnt3 f_cnt2 f_cnt1 f_cnt0 figure 22. 0x00 f_status: fifo status register (read-only) table 15. fifo flag event f_ovf f_wmrk_flag event description 0 ? no fifo overflow events were detected. 1 ? fifo event was detected; the fifo has overflowed. ? 0 no fifo watermark events were detected. ?1 fifo watermark event was detected, which means that the fifo sample count is greater than watermark value. if f_mode = 11, then a trigger event was detected. table 16. fifo sample count register bit(s) field description 5?0 f_cntx[5:0] fifo sample counter indicates the number of acceleration samples currently stored in the fifo buffer. ? count 00_0000 indicates that the fifo is empty. (default value) ? 00_0001 to 10_0000 indicates that 1 to 32 samples are stored in the fifo.
mma8652fc sensors 30 freescale semiconductor, inc. 6.5.2 0x09: f_setup fifo setup register register quick jump table the fifo mode can be changed while in the active mode. the active mode must first be disabled (f_mode = 00), before the mode can be switched between fill mode, circular mode, and trigger mode. a fifo sample count exceeding the watermark event does not stop the fifo from accepting new data. the fifo update rate is dictated by the selected system odr. ? in active mode, the odr is set by the dr bits (ctrl_reg1 register). ? when auto-sleep is active, the odr is set by the aslp_rate field (ctrl_reg1 register). when a byte is read from the fifo buffer, the oldest sample data in the fifo buffer is returned (and also deleted from the fron t of the fifo buffer), while the fifo sample count is decremented by one. it is assumed that the host application will use the i 2 c multi- byte read transaction to empty the fifo. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f_mode1 f_mode0 f_wmrk5 f_wmrk4 f_wmrk3 f_wmrk2 f_wmrk1 f_wmrk0 figure 23. 0x09 f_setup: fifo setup register (read/write) table 17. f_setup register bit(s) field description 7?6 f_mode[1:0] ((1))((2)) 1. bit field can be written in active mode. 2. bit field can be written in standby mode. fifo buffer overflow mode 00 fifo is disabled. (default) 01 fifo contains the most recent samples when overflowed (circular buffer). the oldest sample is discarded and replaced by a new sample. 10 fifo stops accepting new samples when overflowed. 11 trigger mode. the fifo will be in a circular mode up to the number of samples in the watermark. the fifo will be in a circular mode until the trigger event occurs, after which the fifo will continue to accept samples for 32-wmrk samples and then stop receiving further samples. this allows data to be collected both before and after the trigger event, and it is definable by the watermark setting. ? the fifo is flushed whenever the fifo is dis abled, during an automatic odr change (auto-wake/ sleep), or transitioning from standby mode to active mode. ? disabling the fifo (f_mode = 00) resets the f_ovf, f_wmrk_flag, f_cnt to zero. ? a fifo overflow event (i.e., f_cnt = 32) will assert the f_ovf flag and a fifo sample count equal to the sample count watermark (i.e., f_wmrk) asserts the f_wmrk_flag event flag. 5?0 f_wmrk[5:0] (2) fifo event sample count watermark these bits set the number of fifo samples required to trigger a watermark interrupt. a fifo watermark event flag is raised when fifo sample count f_cnt[5:0] f_wmrk[5:0] watermark. ? setting the f_wmrk[5:0] to 00_0000 will disable the fifo watermark event flag generation. ? also used to set the number of pre- trigger samples in trigger mode. 00_0000 (default)
mma8652fc sensors freescale semiconductor, inc. 31 6.5.3 0x0a: trig_cfg trigger configuration register the trigger configuration register configures which interrupt(s) may trigger the fifo. register quick jump table b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 ? ? trig_trans trig_lndprt trig_pulse trig_ff_mt ? ? figure 24. 0x0a: trig_cfg trigger configuration register (read/write) table 18. trigger configuration register bit(s) field description default value notes 5 trig_trans transient interrupt trigger 0 ? these trigger bits set are risi ng-edge sensitive, and are set by a low-to-high state change. ? trigger bits are reset by reading the appropriate source register. 1 this function can trigger the fifo at its (the function?s) interrupt 0 this function has not asserted its interrupt. 4 trig_lndprt landscape/portrait orientation interrupt trigger 0 3 trig_pulse pulse interrupt trigger 0 2 trig_ff_mt freefall/motion trigger 0
mma8652fc sensors 32 freescale semiconductor, inc. 6.6 system status and id registers 6.6.1 0x0b: sysmod system mode register the system mode register indicates the current device operating mode. applications using the auto-sleep/w ake mec hanism should use the sysmod register to synchronize the application with the device operating mode transitions. the sysmod register also indicates the status of the fifo gate error and the number of samples since the gate error occurred. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fgerr fgt_4 fgt_3 fgt_2 fgt_1 fgt_0 sysmod1 sysmod0 figure 25. 0x0b sysmod: system mode register (read-only) table 19. sysmod register bit(s) field description 7fgerr fifo gate error 0 no fifo gate error detected. (default) 1 fifo gate error was detected. emptying the fifo buffer clears the fgerr bit in the sys_mod register. for more information about configuring the fifo gate function, see section 6.13.3, ?0x2c: ctrl_reg3 interrupt control register? . 6?2 fgt[4:0] number of odr time units since fgerr was asserted . reset when fgerr bit is cleared. 0_0000 (default) 1?0 sysmod[1:0] system mode 00 standby mode (default) 01 wake mode 10 sleep mode
mma8652fc sensors freescale semiconductor, inc. 33 6.6.2 0x0c: int_source system interrupt status register in the interrupt source register, the status of the various embedded features can be determined. ? the bits that are set (logic ?1?) indicate which function has asserted an interrupt. ? the bits that are cleared (logic ?0?) indicate which function has not asserted (or has deasserted) an interrupt. int_source register bits are set by a low-to-high transition, an d are cleared by reading the appropriate interrupt source regis ter. for example, the src_drdy bit is cleared when the zyxdr bit (status register) is cleared, but the src_drdy bit is not cleared by simply reading the status register (0x00), but is cleared by reading all the x, y, and z msb data. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 src_aslp src_fifo src_trans src_lndprt src_pulse src_ff_mt ? src_drdy figure 26. 0x0c int_source: system interrupt status register (read only) table 20. int_source register bit(s) field description 7 src_aslp auto-sleep/wake interrupt status bit ? wake-to-sleep transition occurs when no interrupt occurs for a time period that exceeds the user- specified limit (aslp_count). this causes the system to transition to a user-specified low odr setting. ? sleep-to-wake transition occurs when the user-specified in terrupt event has woken the system; thus causing the system to transition to a user-specified high odr setting. ? reading the sysmod register clears the src_aslp bit. 1 an interrupt event that can cause a wake-to-sleep or sleep-to-w ake system m ode transition has occurred. 0 no wake-to-sleep or sleep-to-wake system mode transition interrupt event has occurred. (default) 6src_fifo fifo interrupt status bit ? fifo interrupt event generators: fifo overflow, or (watermark: f_cnt = f_wmrk) and the interrupt has been enabled. ? src_fifo bit is cleared by reading the f_status register. 1 a fifo interrupt event (such as an overflow event or watermark) has occurred. 0 no fifo interrupt event has occurred. (default) 5 src_trans transient interrupt status bit ? src_trans bit is asserted whenever the ea bit (trans_src register) is asserted and the interrupt has been enabled. ? src_trans bit is cleared by reading the trans_src register. 1an acceleration transient value greater than user-specified threshold has occurred. 0 no transient event has occurred. (default) 4 src_lndprt landscape/portrait orientation interrupt status bit ? src_lndprt bit is asserted whenever the newlp bit (pl_status register) is asserted and the interrupt has been enabled. ? src_lndprt bit is cleared by reading the pl_status register. 1 an interrupt was generated due to a change in the device orientation status. 0 no change in orientation status was detected. (default) 3 src_pulse pulse interrupt status bit ? src_pulse bit is asserted whenever the ea bit (pul se_src register) is asserted and the interrupt has been enabled. ? src_pulse bit is cleared by reading the pulse_src register. 1 an interrupt was generated due to single and/or double pulse event. 0 no pulse event was detected. (default) 2 src_ff_mt freefall/motion interrupt status bit ? src_ff_mt bit is asserted whenever the ea bit (ff_mt_src register) is asserted and the ff_mt interrupt has been enabled. ? src_ff_mt bit is cleared by reading the ff_mt_src register. 1 the freefall/motion function interrupt is active. 0 no freefall or motion event was detected. (default)
mma8652fc sensors 34 freescale semiconductor, inc. 0 src_drdy data ready interrupt bit status bit ? src_drdy bit is asserted when the zyxow and/or zyxdr bit is set and the interrupt has been enabled. ? src_drdy bit is cleared by reading the x, y, and z data. 1 the x, y, z data ready interrupt is active (indica ting the presence of new dat a and/or data overrun). 0 the x, y, z interrupt is not active. (default) table 20. int_source register (continued) bit(s) field description
mma8652fc sensors freescale semiconductor, inc. 35 6.6.3 0x0d: who_am_i device id register the device identification register identifies the part. the default value is 0x4a. this value is programmed by freescale before the part leaves the factory. for custom alternate values, contact freescale. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01001 0 1 0 figure 27. 0x0d: who_am_i device id register (read-only)
mma8652fc sensors 36 freescale semiconductor, inc. 6.7 data configuration registers 6.7.1 0x0e: xyz_data_cfg register the xyz_data_cfg register sets the dynamic range and sets the high-pass filter for the output data. when the hpf_out bit is set, the fifo and data registers both will contain high-pass filtered data. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000h p f _ o u t0 0 f s 1f s 0 figure 28. 0x0e: xyz_data_cfg register (read/write) table 21. xyz data configuration register bit(s) field description 4hpf_out enable high-pass output data 1 output data is high-pass filtered. 0 output data is not high-pass filtered. (default) the default full scale value range is 2g and the high-pass filter is disabled. 1?0 fs[1:0] output buffer data format using full scale 00 2g (default) 01, 10, 11 tbd table 22. full scale range fs1 fs0 full scale range 00 2 01 4 10 8 1 1 reserved
mma8652fc sensors freescale semiconductor, inc. 37 6.7.2 0x0f: hp_filter_cutoff high-pass filter register the high-pass filter register sets the high-pass filter cutoff frequency for removal of the offset and slower changing accelera tion data. the output of this filter is logged in the data registers (0x01?0x06) when bit 4 (hpf_out) of register 0x0e is set. the f ilter cutoff options change based on the data rate selected, as shown in table 24 . for more information about the high-pass filter, see application note an4083, data manipulation and basic settings for xtrinsic mma865xfc accelerometers . register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 pulse_hpf_by pulse_lpf_en 0 0 sel1 sel0 figure 29. 0x0f hp_filter_cutoff: high-pass filter register (read/write) table 23. high-pass filter cutoff register bit(s) field description 5 pulse_hpf_byp bypass high-pass filter (hpf) for pulse processing function 0 hpf is enabled for pulse processing (default) 1 hpf is bypassed for pulse processing 4 pulse_lpf_en enable low-pass filter (lpf) for pulse processing function 0 lpf is disabled for pulse processing (default) 1 lpf is enabled for pulse processing 1?0 sel[1:0] hpf cutoff frequency selection 00 (default value, see table 24 ) 01, 10, 11 tbd table 24. high-pass filter cutoff options sel1 sel0 800 hz 400 hz 200 hz 100 hz 50 hz 12.5 hz 6.25 hz 1.56 hz oversampling mode = normal 0 0 16 hz 16 hz 8 hz 4 hz 2 hz 2 hz 2 hz 2 hz 0 1 8 hz 8 hz 4 hz 2 hz 1 hz 1 hz 1 hz 1 hz 1 0 4 hz 4 hz 2 hz 1 hz 0.5 hz 0.5 hz 0.5 hz 0.5 hz 1 1 2 hz 2 hz 1 hz 0.5 hz 0.25 hz 0.25 hz 0.25 hz 0.25 hz oversampling mode = low noise low power 0 0 16 hz 16 hz 8 hz 4 hz 2 hz 0.5 hz 0.5 hz 0.5 hz 0 1 8 hz 8 hz 4 hz 2 hz 1 hz 0.25 hz 0.25 hz 0.25 hz 1 0 4 hz 4 hz 2 hz 1 hz 0.5 hz 0.125 hz 0.125 hz 0.125 hz 1 1 2 hz 2 hz 1 hz 0.5 hz 0.25 hz 0.063 hz 0.063 hz 0.063 hz oversampling mode = high resolution 0 0 16 hz 16 hz 16 hz 16 hz 16 hz 16 hz 16 hz 16 hz 0 1 8 hz 8 hz 8 hz 8 hz 8 hz 8 hz 8 hz 8 hz 1 0 4 hz 4 hz 4 hz 4 hz 4 hz 4 hz 4 hz 4 hz 1 1 2 hz 2 hz 2 hz 2 hz 2 hz 2 hz 2 hz 2 hz oversampling mode = low power 0 0 16 hz 8 hz 4 hz 2 hz 1 hz 0.25 hz 0.25 hz 0.25 hz 0 1 8 hz 4 hz 2 hz 1 hz 0.5 hz 0.125 hz 0.125 hz 0.125 hz 1 0 4 hz 2 hz 1 hz 0.5 hz 0.25 hz 0.063 hz 0.063 hz 0.063 hz 1 1 2 hz 1 hz 0.5 hz 0.25 hz 0.125 hz 0.031 hz 0.031 hz 0.031 hz
mma8652fc sensors 38 freescale semiconductor, inc. 6.8 portrait/landscape configur ation and status registers for more information about the different user-configurable settings and example code, see application note an4083, data manipulation and basic settings for xt rinsic mma865xfc accelerometers . 6.8.1 0x10: pl_status portrait/landscape status register to get updated information on any change in orientation, read the portrait/landscape status register (read bit 7, or read the o ther bits for more orientation data). for more about portrait up, portrait down, landscape left, landscape right, back, and front orientations, see figure 3 . the interrupt is cleared when reading the pl_status register. register quick jump table ? the orientation mechanism state change is limited to a maximum 1.25g. the current position is locked if the absolute value of the acceleration experienced on any of the three axes is greater than 1.25g. ? lapo, bafro, and lo continue to change when newlp is set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 newlp lo ? ? ? lapo[1] lapo[0] bafro figure 30. 0x10 pl_status register (read-only) table 25. pl_status register bit(s) field description 7newlp landscape/portrait status change flag ? newlp is set to 1 after the first orientation detec tion after a standby-to-active transition, and whenever a change in lo, bafro, or lapo occurs. ? newlp bit is cleared anytime pl_status register is read. 0 no change (default) 1 bafro and/or lapo and/or z-tilt lockout value has changed 6l o z-tilt angle lockout 0 lockout condition has not been detected (default) 1 z-tilt lockout trip angle has been exceeded. lockout has been detected. 2?1 lapo[1:0] (1) 1. the default power-up state is bafro = 0, lapo = 00, and lo = 0 . landscape/portrait orientation 00 portrait up: equipment standing vertically in the normal orientation (default) 01 portrait down: equipment standing vertically in the inverted orientation 10 landscape right: equipment is in landscape mode to the right 11 landscape left: equipment is in landscape mode to the left. 0bafro back or front orientation 0 front: equipment is in the fr ont-facing orientation (default) 1 back: equipment is in the back-facing orientation
mma8652fc sensors freescale semiconductor, inc. 39 6.8.2 0x11 portrait/landscape configuration register the portrait/landscape configuration register enables the portrait/landscape function and sets the behavior of the debounce counter. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm pl_en ? ? ? ? ? ? figure 31. 0x11 pl_cfg register (read/write) table 26. pl_cfg register bit(s) field description 7dbcntm debounce counter mode selection 0 decrements debounce whenever the condition of interest is no longer valid. 1 clears the counter whenever the condition of interest is no longer valid. (default) 6 pl_en portrait/landscape detection enable 0 portrait/landscape detection is disabled. (default) 1 portrait/landscape detection is enabled.
mma8652fc sensors 40 freescale semiconductor, inc. 6.8.3 0x12 portrait/landscape debounce register the portrait/landscape debounce register sets the debounce count for the orientation state transition. the minimum debounce latency is determined by the data rate (which is set by the product of the selected system odr and pl_count registers). any transition from wake to sleep (or sleep to wake) resets the internal landscape/portrait debounce counter. note the debounce counter weighting (time step) changes, based on the odr and the oversampling mode. table 28 explains the time step value for all sample rates and all oversampling modes. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbnce[7] dbnce[6] dbnce[5] dbnce[4] dbnce[3] dbnce[2] dbnce[1] dbnce[0] figure 32. 0x12 pl_count register (read/write) table 27. pl_count register bit(s) field description 7?0 dbcne[7:0] debounce count value 0000_0000 (default) table 28. pl_count relationship with the odr odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160
mma8652fc sensors freescale semiconductor, inc. 41 6.8.4 0x13: pl_bf_zcomp back/front and z compensation register the z-lock angle compensation bits allows you to adjust the z-lockout region from 14 up to 43. on power-up, the default z-lo ckout angle is set to the default value of 29. the back-to-front trip angle is set by default to 75, and this angle can be adjuste d from a range of 65 to 80 (with 5 step increments). register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bkfr[1] bkfr[0] ? ? ? zlock[2] zlock[1] zlock[0] figure 33. 0x13: pl_bf_zcomp register (read/write) table 29. pl_bf_zcomp register bit(s) field description notes 7?6 bkfr[7:6] back/front trip angle threshold ? step size = 5 ? range = (65 to 80) 01 75 (default) all angles are accurate to 2. 2?0 zlock[2:0] z-lock sngle threshold ? step size is 4 ? range is from 14 to 43 100 29 (default) 111 43 (maximum) table 30. z-lock threshold angles z-lock value threshold angle 0x00 14 0x01 18 0x02 21 0x03 25 0x04 29 0x05 33 0x06 37 0x07 42 table 31. back/front orientation definitions bkfr back/front transition front/back transition 00 z < 80 or z > 280 z > 100 and z < 260 01 z < 75 or z > 285 z > 105 and z < 255 10 z < 70 or z > 290 z > 110 and z < 250 11 z < 65 or z > 295 z > 115 and z < 245
mma8652fc sensors 42 freescale semiconductor, inc. 6.8.5 0x14: p_l_ths_reg portrait/landscape threshold and hysteresis register this register represents the portrait-to-landscape trip threshold register used to set the trip angle for transitioning from po rtrait to landscape mode and from landscape to portrait mode. this register includes a value for the hysteresis. table 33 is a look-up table to set the threshold. this is the center value that will be set for the trip point from portrait to landsca pe and from landscape to portrait. the default trip angle is 45 (0x10). the default hysteresis is 14. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] hys[2] hys[1] hys[0] figure 34. 0x14: p_l_ths_reg register (read/write) table 32. p_l_ths_reg register bit(s) field description notes 7?3 p_l_ths[7:3] portrait/landscape trip threshold angle (from 15 to 75) see table 33 for the values with the corresponding approximate threshold angle. 1_0000 (45) (default) for the landscape/portrait detection to work correctly, ths + hys > 0 and ths + hys < 32. all angles are accurate to 2. 2?0 hys[2:0] hysteresis value this angle is added to the threshold angle, for a smoother transition from portrait to landscape and landscape to portrait. this angle ranges from 0 to 24. 100 (14) (default) table 33. threshold angle thresholds look-up table threshold angle (approximately) 5-bit register value 15 0x07 20 0x09 30 0x0c 35 0x0d 40 0x0f 45 0x10 55 0x13 60 0x14 70 0x17 75 0x19 table 34. trip angles with hysteresis for 45 angle hysteresis register value hysteresis angle range landscape-to-portrait trip angle portrait-to-landscape trip angle 0 0 45 45 1 4 49 41 2 7 52 38 3 11 56 34 4 14 59 31 5 17 62 28 6 21 66 24 7 24 69 21
mma8652fc sensors freescale semiconductor, inc. 43 6.9 freefall/motion configur ation and status registers the freefall/motion function can be configured in either freefall or motion detection mode via the oae configuration bit (0x15: ff_mtg_cfg, bit 6). the freefall/motion detection block can be disabled by setting all three bits zefe, yefe, and xefe to zero. depending on the register bits ele (0x15: ff_mtg_cfg, bit 7) and oae (0x15: ff_mtg_cfg, bit 6), each of the freefall and motion detection block can operate in four different modes. 6.9.1 motion and freefall modes 6.9.1.1 mode 1: freefall detection with ele = 0, oae = 0 in this mode, the ea bit (0x16: ff_mtg_cfg, bit 7) indicates a freefall event after the debounce counter is complete . the zefe, yefe, and xefe control bits determine which axes are considered for the freefall detection. once the ea bit is set, and dbcntm = 0, the ea bit can get cleared only after the delay specified by ff_mt_count. this is because the counter is in decrement mode. if dbcntm = 1, then the ea bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by ff_mt_count has passed. reading the ff_mt_src register does not clear the ea bit. the event flags (0x16) zhe, zhp, yhe, yhp, xhe, and xhp reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits zefe, yefe, and/or xefe are set. 6.9.1.2 mode 2: freefall detection with ele = 1, oae = 0 in this mode, the ea event bit indicates a freefall event after the debounce counter . once the debounce counter reaches the time value for the set threshold, the ea bit is set, and the ea bit remains set until the ff_mt_src register is read. when the ff_mt_src register is read, the ea bit and the debounce counter are cleared, and a new event can only be generated after the delay specified by ff_mt_cnt. the zefe, yefe, and xefe control bits determine which axes are considered for the freefall detection. while ea = 0, the event flags zhe, zhp, yhe, yhp, xhe, and xhp reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits zefe, yefe, and/or xefe are set. the event flags zhe, zhp, yhe, yhp, xhe, and xhp are latched when the ea event bit is set. the event flags zhe, zhp, yhe, yhp, xhe, and xhp will start changing only after the ff_mt_src register has been read. 6.9.1.3 mode 3: motion detection with ele = 0, oae = 1 in this mode, the ea bit indicates a motion event after the debounce counter time is reached . the zefe, yefe, and xefe control bits determine which axes are taken into consideration for motion detection. once the ea bit is set and if dbcntm = 0, the ea bit can get cleared only after the delay specified by ff_mt_count. if dbcntm = 1, then the ea bit is cleared as soon as the motion high g condition disappears. the event flags zhe, zhp, yhe, yhp, xhe, and xhp reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits zefe, yefe, and/or xefe are set. reading the ff_mt_src does not clear any flags, nor is the debounce counter reset. 6.9.1.4 mode 4: motion detection with ele = 1, oae = 1 in this mode, the ea bit indicates a motion event after debouncing . the zefe, yefe, and xefe control bits determine which axes are taken into consideration for motion detection. once the debounce counter reaches the threshold, the ea bit is set, and the ea bit remains set until the ff_mt_src register is read. when the ff_mt_src register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by ff_mt_cnt. while the bit ea is zero, the event flags zhe, zhp, yhe, yhp, xh e, and xhp reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits zefe, yefe, and/or xefe are set. when the ea bit is set, these bits (zhe, zhp, yhe, yhp, xhe, xhp) keep their current value until the ff_mt_src register is read.
mma8652fc sensors 44 freescale semiconductor, inc. 6.9.2 0x15: ff_mt_cfg freefall/motion configuration register this is the freefall/motion configuration register for setting up the conditions of the freefall or motion function. register quick jump table figure 36. ff_mt_cfg high and low g level bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ele oae zefe yefe xefe ? ? ? figure 35. 0x15 ff_mt_cfg register (read/write) table 35. ff_mt_cfg register bit(s) field description 7ele event latch enable : event flags are latched into ff_mt_src register. ele denotes whether the enabled event flag will to be latched in to the ff_mt_src register or whether the event flag status in the ff_mt_src will indicate the real-time status of the event. ? if ele bit is set to 1, then the event flags are frozen when the ea bit gets set, and the event flags are cleared by reading the ff_mt_src source register. ? reading the ff_mt_src register clears the event flag ea and all ff_mt_src bits. 0 event flag latch disabled (default) 1 event flag latch enabled 6oae motion detect / freefall detect flag selection selects between motion (logical or combination) and freefall (logical and combination) detection. 0 freefall flag (logical and combination) (default) 1 motion flag (logical or combination) 5zefe event flag enable on z zhfe enables the detection of a motion or freefall event when the measured acceleration data on z channel is beyond the threshold set in ff_mt_ths register. ? if ele bit (ff_mt_cfg register) is set to 1, then new event flags are blocked from updating the ff_mt_src register. 0 event detection disabled (default) 1 raise event flag on measured acceleration value beyond preset threshold 4yefe event flag enable on y event yefe enables the detection of a motion or freefall event when the measured acceleration data on y channel is beyond the threshold set in ff_mt_ths register. ? if ele bit (ff_mt_cfg register) is set to 1, then new event flags are blocked from updating the ff_mt_src register. 0 event detection disabled (default) 1 raise event flag on measured acceleration value beyond preset threshold 3xefe event flag enable on x event xefe enables the detection of a motion or freefall event when the measured acceleration data on x channel is beyond the threshold set in ff_mt_ths register. ? if ele bit (ff_mt_cfg register) is set to 1, then new event flags are blocked from updating the ff_mt_src register. 0 event detection disabled (default) 1 raise event flag on measured acceleration value beyond preset threshold +8g high-g + threshold (motion) low-g threshold (freefall) high-g - threshold (motion) -8g x, y, z high-g region x, y, z high-g region x, y, z low-g region negative positive acceleration acceleration
mma8652fc sensors freescale semiconductor, inc. 45 6.9.3 0x16: ff_mt_src freefall/motion source register the freefall/motion source register keeps track of the acceleration event that is triggering (or has triggered, if ele bit in ff_mt_cfg register is set to 1) the event flag. in particular, ea is set to 1 when the logical combination of acceleration even ts flags specified in ff_mt_cfg register is true. this ea bit is used in combination with the values in int_en_ff_mt and int_cfg_ff_mt register bits to generate the freefall/motion interrupts. ? an x,y, or z motion is true when the acceleration value of the x or y or z channel is higher than the preset threshold value defined in the ff_mt_ths register. ? an x, y, and z low event is true when the acceleration value of the x and y and z channel is lower than or equal to the preset threshold value defined in the ff_mt_ths register. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ea ? zhe zhp yhe yhp xhe xhp figure 37. 0x16: ff_mt_src freefall/m otion source register (read-only) table 36. freefall/motion source register bit(s) field description 7e a event active flag 0 no event flag has been asserted (default) 1 one or more event flags has been asserted. see the description of the oae bit to determine the effect of the 3-axis event flags on the ea bit. 5z h e z motion flag zhe bit always reads zero if the zefe control bit is set to zero. 0 no z motion event detected (default) 1 z motion has been detected 4z h p z motion polarity flag zhp bit always reads zero if the zefe control bit is set to zero. 0 z event was positive g (default) 1 z event was negative g 3y he y motion flag yhe bit always reads zero if the yefe control bit is set to zero. 0 no y motion event detected (default) 1 y motion has been detected 2y hp y motion polarity flag yhp bit always reads zero if the yefe control bit is set to zero. 0 y event detected was positive g (default) 1 y event was negative g 1x he x motion flag xhe bit always reads zero if the xefe control bit is set to zero. 0 no x motion event detected (default) 1 x motion has been detected 0x hp x motion polarity flag xhp bit always reads zero if the xefe control bit is set to zero. 0 x event was positive g (default) 1 x event was negative g
mma8652fc sensors 46 freescale semiconductor, inc. 6.9.4 0x17: ff_mt_ths freefall and motion threshold register ff_mt_ths is the threshold register used to detect freefall motion events. ? the unsigned 7-bit ff_mt_ths threshold register holds the threshold for the freefall detection where the magnitude of the x and y and z acceleration values is lower or equal than the threshold value . ? conversely, the ff_mt_ths also holds the threshold for the motion detection where the magnitude of the x or y or z acceleration value is higher than the threshold value . register quick jump table the threshold resolution is 0.063g/lsb and the threshold register has a range of 0 to 127 counts. the maximum range is to 8g. note that even when the full scale value is set to 2g or 4g, the motion still detects up to 8g. the dbcntm bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not true. ? when dbcntm bit is 1 , the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true as shown in figure 40 , (b). ? while the dbcntm bit is set to 0 , the debounce counter is decremented by 1 whenever the inertial event of interest is no longer true ( figure 40 , (c)) until the debounce counter reaches 0 or until the inertial event of interest becomes active. decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events (which might impede the detection of inertial events). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 figure 38. 0x17 ff_mt_ths register (read/write) table 37. ff_mt_ths register bit(s) field description 7dbcntm debounce counter mode selection 0 increments or decrements debounce (default) 1 increments or clears counter. 6?0 ths[6:0] freefall /motion threshold 000_0000 (default)
mma8652fc sensors freescale semiconductor, inc. 47 6.9.5 0x18 ff_mt_count debounce register the debounce register sets the number of debounce sample counts for the event trigger. register quick jump table the debounce register sets the minimum number of debounce sample counts that continuously match the detection condition selected by you for the freefall/motion event. when the internal debounce counter reaches the ff_mt_count value, a freefall/motion event flag is set. the debounce counter will never increase beyond the ff_mt_count value. the time step used for the debounce sample count depends on the odr chosen and the oversampling mode, as shown in table 39 . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 39. 0x18 ff_mt_count register (read/write) table 38. ff_mt_count register bit(s) field description 7?0 d[7:0] count value 0000_0000 (default) table 39. ff_mt_count relationship with the odr odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160
mma8652fc sensors 48 freescale semiconductor, inc. figure 40. dbcntm bit function high g event on count threshold ff ffea all 3-axis (motion detect) counter value high g event on count threshold debounce (a) all 3-axis (motion detect) counter value high g event on count threshold debounce ea all 3-axis (motion detect) counter value dbcntm = 1 (b) ea dbcntm = 0 (c)
mma8652fc sensors freescale semiconductor, inc. 49 6.10 transient configuratio n and status registers for more information about the uses of the transient function, see application note an4083, data manipulation and basic settings for xtrinsic mma865xfc accelerometers . this transient (hpf) acceleration detection function is similar to the motion detection function, except that high-pass filtered data is compared. there is an option to disable the high-pass filter through the function. in this case, the behavior is the same as the motion detection. this allows for the device to have two motion detection functions. 6.10.1 0x1d: transient_cfg register the transient detection mechanism can be configured to raise an interrupt when the magnitude of the high-pass filtered acceleration threshold is exceeded. the transient_cfg register is used to enable the transient interrupt generation mechanism for the three axes (x, y, z) of acceleration. there is also an option to bypass the high-pass filter. when the high-p ass filter is bypassed, the function behaves similar to the motion detection. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ele ztefe ytefe xtefe hpf_byp figure 41. 0x1d transient_cfg register (read/write) table 40. transient_cfg register bit(s) field description notes 4ele transient event flags are latched into the transient_src register . reading of the transient_src register clears the event flag. 0 event flag latch disabled (default) 1 event flag latch enabled 3 ztefe event flag enable for z-transient acceleration greater than a transient threshold event . 0 event detection disabled (default) 1 raise event flag on measured acceleration delta value that is greater than a transient threshold. 2 ytefe event flag enable for y-transient acceleration greater than a transient threshold event . 1 xtefe event flag enable for x-transient acceleration greater than a transient threshold event . 0hpf_byp bypass high-pass filter 0 data to transient acceleration detection block is through hpf (default) 1 data to transient acceleration detection block is not through hpf (similar to motion detection function)
mma8652fc sensors 50 freescale semiconductor, inc. 6.10.2 0x1e transient_src register the transient source register provides the status of the enabl ed axes and the polarity (directional) information. when the transient_src register is read, it clears the interrupt for the transient detection. when new events arrive while ea = 1, additional *transe bits may get set, and the corresponding *_trans_pol flag become updated. however no *transe bit may get cleared before the transient_src register is read. register quick jump table ? when the ea bit gets set while ele = 1, all other status bits get frozen at their current state. ? by reading the transient_src register, all bits get cleared. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ea ztranse z_trans_pol ytranse y _trans_pol xtranse x_trans_pol figure 42. 0x1e transient_src register (read-only) table 41. transient_src register bit(s) field description 6e a event active flag 0 no event flag has been asserted (default) 1 one or more event flags has been asserted. 5 ztranse z transient event 0 no interrupt (default) 1 z transient acceleration greater than the value of transient_ths event has occurred 4 z_trans_pol polarity of z transient event that triggered the interrupt 0 z event was positive g (default) 1 z event was negative g 3ytranse y transient event 0 no interrupt (default) 1 y transient acceleration greater than the value of transient_ths event has occurred 2 y_trans_pol polarity of y transient event that triggered the interrupt 0 y event was positive g (default) 1 y event was negative g 1xtranse x transient event 0 no interrupt (default) 1 x transient acceleration greater than the value of transient_ths event has occurred 0 x_trans_pol polarity of x transient event that triggered the interrupt 0 x event was positive g (default) 1 x event was negative g
mma8652fc sensors freescale semiconductor, inc. 51 6.10.3 0x1f transient_ths register the transient threshold register sets the threshold limit for the detection of the transient acceleration. the value in the transient_ths register corresponds to a g value, which is compared against the values of high-pass filtered data. if the high- pass filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated (if enable d). register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 figure 43. 0x1f transient_ths register (read/write) table 42. transient_ths register bit(s) field description notes 7dbcntm debounce counter mode selection 0 increments or decrements debounce (default) 1 increments or clears counter 6?0 ths[6:0] transient threshold a 7-bit unsigned number, with 0.063g/lsb. the maximum threshold is 8g. 000_0000 (default) even if the part is set to full scale at 2g (or 4g), this function will still operate up to 8g.
mma8652fc sensors 52 freescale semiconductor, inc. 6.10.4 0x20 transient_count register the transient_count sets the minimum number of debounce counts continuously matching the condition where the unsigned value of high-pass filtered data is greater than the user-specified value of transient_ths. register quick jump table the time step for the transient detection debounce counter is set by the value of the system odr and the oversampling mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 44. 0x20 transient_count register (read/write) table 43. transient_count register bit(s) field description 7?0 d[7:0] count value 0000_0000 (d efault) table 44. transient_count relationship with the odr odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160
mma8652fc sensors freescale semiconductor, inc. 53 6.11 pulse configuration and status registers for more information about of how to configure the tap detection and sample code, see application note an4083, data manipulation and basic settings for xtrinsic mma865xfc accelerometers . the tap detection registers are referred to as ?pulse?. 6.11.1 0x21: pulse_cfg pulse configuration register the pulse_cfg register configures the event flag for tap detection, enabling/disabling the detection of a single and double pulse on each of the axes. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dpa ele zdpefe zspefe ydpefe yspefe xdpefe xspefe figure 45. 0x21 pulse_cfg register (read/write) table 45. pulse_cfg register bit(s) field description notes 7dpa double pulse abort 0 double pulse detection is not aborted if the start of a pulse is detected during the time period specified by the pulse_ltcy register. (default) 1 setting the dpa bit momentarily suspends the double tap detection if the start of a pulse is detected during the time period specified by the pulse_ltcy register, and the pulse ends before the end of the time period specified by the pulse_ltcy register. 6ele pulse event flags are latched into the pulse_src register . reading of the pulse_src register clears the event flag. 0 event detection is disabled (default) 1 event detection is enabled 5zdpefe event flag enable for a double pulse event on z-axis 4 zspefe event flag enable for a single pulse event on z-axis 3ydpefe event flag enable for a double pulse event on y-axis 2 yspefe event flag enable for a single pulse event on y-axis 1xdpefe event flag enable for a double pulse event on x-axis 0 xspefe event flag enable for a single pulse event on x-axis
mma8652fc sensors 54 freescale semiconductor, inc. 6.11.2 0x22: pulse_src pulse source register the pulse_src register indicates a double or single pulse event has occurred (and also which direction). the corresponding axis and event must be enabled in register 0x21 for the event flag to be asserted in the source register. register quick jump table ? when the ea bit gets set while ele = 1, all status bits (axz, axy, axz, dpe, and polx, poly, polz) are frozen. ? reading the pulse_src register clears all bits. ? reading the source register will clear the interrupt. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ea axz axy axx dpe polz poly polx figure 46. 0x22 pulse_src register (read-only) table 46. pulse_src register bit field description 7ea event active flag 0 no interrupt has been generated (default) 1 one or more interrupt events have been generated 6axz z-axis event 0 no interrupt (default) 1 z-axis event has occurred 5axy y-axis event 0 no interrupt (default) 1 y-axis event has occurred) 4axx x-axis event 0 no interrupt (default) 1 x-axis event has occurred 3dpe double pulse on first event 0 single pulse event triggered interrupt (default) 1 double pulse event triggered interrupt 2polz pulse polarity of z-axis event 0 pulse event that triggered interrupt was positive (default) 1 pulse event that triggered interrupt was negative) 1poly pulse polarity of y-axis event 0 pulse event that triggered interrupt was positive (default) 1 pulse event that triggered interrupt was negative 0polx pulse polarity of x-axis event 0 pulse event that triggered interrupt was positive (default) 1 pulse event that triggered interrupt was negative
mma8652fc sensors freescale semiconductor, inc. 55 6.11.3 0x23 ? 0x25: pulse_thsx, y, z pulse threshold for x, y and z registers the pulse threshold can be set separately for the x, y, and z axes. the pulse_thsx, pulse_thsy and pulse_thsz registers define the threshold that is used by the system to start the pulse detection procedure. register quick jump table ? the threshold values range from 1 to 127, with steps of 0.63g/lsb at a fixed 8g acceleration range, thus the minimum resolution is always fixed at 0.063g/lsb. ? the pulse_thsx, pulse_thsy and pulse_thsz registers define the threshold which is used by the system to start the pulse detection procedure. ? the threshold value is expressed over 7-bits as an unsigned number. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 figure 47. 0x23 pulse_thsx register (read/write) table 47. pulse_thsx register bit(s) field description 6?0 thsx[6:0] pulse threshold on x-axis 000_0000 (default) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 figure 48. 0x24 pulse_thsy register (read/write) table 48. pulse_thsy register bit(s) field description 6?0 thsy[6:0] pulse threshold on y-axis 000_0000 (default value) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 figure 49. 0x25 pulse_thsz register (read/write) table 49. pulse_thsz register bit(s) field description 6?0 thsz[6:0] pulse threshold on z-axis 000_0000 (default)
mma8652fc sensors 56 freescale semiconductor, inc. 6.11.4 0x26: pulse_tmlt pulse time window 1 register register quick jump table bits tmlt7 ? tmlt0 define the maximum time interval that can elapse between the start of the acceleration on the selected axis exceeding the specified threshold, and the end when the acceleration on the selected axis must go below the specified threshold to be considered a valid pulse. the minimum time step for the pulse time limit is defined in table 51 and table 52 . ? maximum time for a given odr and oversampling mode is the time step pulse multiplied by 255. ? the time steps available are dependent on the oversampling mode and whether the pulse low-pass filter option is enabled or not. ? the pulse low-pass filter is set in register 0x0f. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmlt7 tmlt6 tmlt5 tmlt4 tmlt3 tmlt2 tmlt1 tmlt0 figure 50. 0x26 pulse_tmlt register (read/write) table 50. pulse_tmlt register bit(s) field description 7?0 tmlt[7:0] pulse time limit 0000_0000 (default) table 51. time step for pulse time limit (reg 0x0f) pulse_lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.56 5.1 20.4 0.638 40.8 20 80 2.5 160 table 52. time step for pulse time limit (reg 0x0f) pulse_lpf_en = 0 odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.159 0.159 0.159 0.159 0.625 0.625 0.625 0.625 400 0.159 0.159 0.159 0.319 0.625 0.625 0.625 1.25 200 0.319 0.319 0.159 0.638 1.25 1.25 0.625 2.5 100 0.638 0.638 0.159 1.28 2.5 2.5 0.625 5 50 1.28 1.28 0.159 2.55 5 5 0.625 10 12.5 1.28 5.1 0.159 10.2 5 20 0.625 40 6.25 1.28 5.1 0.159 10.2 5 20 0.625 40 1.56 1.28 5.1 0.159 10.2 5 20 0.625 40
mma8652fc sensors freescale semiconductor, inc. 57 6.11.5 0x27: pulse_ltcy pulse latency timer register register quick jump table bits ltcy7 ? ltcy0 define the time interval that starts after the first pulse detection. during this time interval, all pulses are ignored. note this timer must be set for single pulse and for double pulse. the minimum time step for the pulse latency is defined in table 54 and table 55 . ? the maximum time is the time step at the odr and oversampling mode multiplied by 255. ? the timing also changes when the pulse lpf is enabled or disabled. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ltcy7 ltcy6 ltcy5 ltcy4 ltcy3 ltcy2 ltcy1 ltcy0 figure 51. 0x27 pulse_ltcy register (read/write) table 53. pulse_ltcy register bit(s) field description 7?0 ltcy[7:0] latency time limit 0000_0000 (default) table 54. time step for pulse latency at odr and power mode (reg 0x0f) pulse_lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 4 0 01 . 2 7 61 . 2 7 61 . 2 7 61 . 2 7 65555 200 2.56 2.56 1.276 2.56 10 10 5 10 100 5.1 5.1 1.276 5.1 20 20 5 20 50 10.2 10.2 1.276 10.2 40 40 5 40 12.5 10.2 40.8 1.276 40.8 40 160 5 160 6.25 10.2 40.8 1.276 81.6 40 160 5 320 1.56 10.2 40.8 1.276 81.6 40 160 5 320 table 55. time step for pulse latency at odr and power mode (reg 0x0f) pulse_lpf_en = 0 odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.25 2.56 10.2 0.318 20.4 10 40 1.25 80 1.56 2.56 10.2 0.318 20.4 10 40 1.25 80
mma8652fc sensors 58 freescale semiconductor, inc. 6.11.6 0x28 pulse_wind register (read/write) register quick jump table bits wind7 ? wind0 define the maximum interval of time that can elapse after the end of the latency interval, in which the star t of the second pulse event must be detected (provided the device has been configured for double pulse detection). the detected second pulse width must be shorter than the time limit constraints specified by the pulse_tmlt register, but the end of the double pulse need not finish within the time specified by the pulse_wind register. the minimum time step for the pulse window is defined in table 57 and table 58 . the maximum time is the time step at the odr, oversampling mode and lpf filter option multiplied by 255. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wind7 wind6 wind5 wind4 wind3 wind2 wind1 wind0 figure 52. 0x28: pulse_wind second pulse time window register table 56. pulse_wind register bit(s) field description 7?0 wind[7:0] second pulse time window 0000_0000 (default value) table 57. time step for pulse detection window at odr and power mode (reg 0x0f) pulse_lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 400 1.276 1.276 1.276 1.276 5 5 5 5 200 2.56 2.56 1.276 2.56 10 10 5 10 100 5.1 5.1 1.276 5.1 20 20 5 20 50 10.2 10.2 1.276 10.2 40 40 5 40 12.5 10.2 40.8 1.276 40.8 40 160 5 160 6.25 10.2 40.8 1.276 81.6 40 160 5 320 1.56 10.2 40.8 1.276 81.6 40 160 5 320 table 58. time step for pulse detection window at odr and power mode (reg 0x0f) pulse_lpf_en = 0 odr (hz) max time range (s) time step (ms) normal lpln highres lp normal lpln highres lp 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.25 2.56 10.2 0.318 20.4 10 40 1.25 80 1.56 2.56 10.2 0.318 20.4 10 40 1.25 80
mma8652fc sensors freescale semiconductor, inc. 59 6.12 auto-wake/sleep register 6.12.1 0x29: aslp_count, auto-wake/sleep detection register (read/write) the aslp_count register sets the minimum time period of inactivity required to switch the part between wake and sleep status. at the end of the time period, the device switches its odr rate automatically when the auto-wake /sleep function is enabled. ? wake odr is set by ctrl_reg1[dr] bits. ? sleep odr is set by ctrl_reg1[aslp_rate] bits. ? auto wake/sleep function is enabled by asserting the ctrl_reg2[slpe] bit. register quick jump table d7?d0 defines the minimum duration time needed to change the current odr value from dr to aslp_rate . the time step and maximum value depend on the odr chosen (as shown in table 60 ). for functional blocks that may be monitored for inactivity (to trigger the ?return to sleep? event), see table 61 . ? 4 interrupt sources can wake the device: transient, orientation, tap, and the motion/freefall. one or more of these functions can be enabled. ? to wake the device, the desired function(s) must be en abled in ctrl_reg4 register and set to wake-to-sleep in ctrl_reg3 register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 53. 0x29 aslp_count register (read/write) table 59. aslp_count register bit(s) field description 7?0 d[7:0] duration value 0000_0000 (default) table 60. aslp_count relationship with odr output data rate (odr) duration (sec) odr time step (ms) aslp_count step (ms) 800 hz 0 to 81 1.25 320 400 hz 0 to 81 2.5 320 200 hz 0 to 81 5 320 100 hz 0 to 81 10 320 50 hz 0 to 81 20 320 12.5 hz 0 to 81 80 320 6.25 hz 0 to 81 160 320 1.56 hz 0 to 162 640 640 table 61. sleep/wake mode gates and triggers interrupt source will the event restart the timer and delay ?return to sleep?? will the event wake from sleep? notes fifo_gate yes no * if the fifo_gate bit is set to 1, then the assertion of the src_aslp interrupt does not prevent the system from transitioning to sleep or from wake mode; instead the assertion of the interrupt prevents the fifo buffer from accepting new sample data?until the host application flushes the fifo buffer. src_trans yes yes src_lndprt yes yes src_pulse yes yes src_ff_mt yes yes src_aslp no* no* src_drdy no no
mma8652fc sensors 60 freescale semiconductor, inc. ? all enabled functions still run in sleep mode at the sleep odr. only the functions that have been selected for wake from sleep will actually wake the device (as configured in register 0x2c). ? note that the fifo does not wake the device. ? the auto-wake/sleep interrupt does not affect the wake/sleep, nor does the data ready interrupt. ? when set to 1, the fifo gate (bit 7 in register 0x2c) will hold the last data in the fifo, before transitioning to a different odr. after the buffer is flushed, it will accept new sample data at the current odr. see register 0x2c for the wake-from-sleep interrupt enable bit definitions. ? mma8652fc has 4 functions that can be used to keep the sensor from falling asleep: transient, orientation, tap and motion/ freefall. ? auto-sleep bit: ? if the auto-sleep bit is disabled, then the device can only toggle between standby and wake mode. ? if auto-sleep interrupt is enabled, then transitioning from active mode to auto-sleep mode (or vice versa) generates an interrupt.
mma8652fc sensors freescale semiconductor, inc. 61 6.13 system and control registers note except for standby mode selection, the device must be in standby mode to change any of the fields within ctrl_reg1 (0x2a). 6.13.1 0x2a: ctrl_reg1 system control 1 register ctrl_reg1 register configures the auto-wake sample frequency, output data rate selection, and enables the fast-read mode and standby/active mode selection. register quick jump table dr[2:0] bits select the output data rate (odr) for acceleration samples in wake mode. the default value is 000 for a data rate of 800 hz. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aslp_rate1 aslp_rate0 dr2 dr1 dr0 ? f_read active figure 54. 0x2a ctrl_reg1 register (read/write) table 62. ctrl_reg1 register bit(s) field description 7?6 aslp_rate[1:0] configures the auto-wake sample frequency when the device is in sleep mode . see table 63 . 00 (default) 5?3 dr[2:0] data rate selection see table 64 . 000 (default) 1f _ r e a d fast-read mode : data format is limited to single byte 0 normal mode (default) 1 fast read mode 0a c t i v e full-scale selection 0 standby mode (default) 1 active mode table 63. sleep mode rates aslp_rate1 aslp_rate0 frequency (hz) notes 00 5 0 when the device is in auto-sleep mode, the system odr and the data rate for all the system functional blocks are overridden by the data rate set by the aslp_rate field. 0 1 12.5 1 0 6.25 1 1 1.56 table 64. system output data rate selection dr2 dr1 dr0 odr (hz) period (ms) notes 0 0 0 800 1.25 default 0 0 1 400 2.5 0 1 0 200 5 0 1 1 100 10 1 0 0 50 20 1 0 1 12.5 80 1 1 0 6.25 160 1 1 1 1.56 640
mma8652fc sensors 62 freescale semiconductor, inc. the active bit selects between standby mode and active mode. ? the f_read bit selects between normal and fast read mode. when selected, the auto-increment counter will skip over the lsb data bytes. data read from the fifo will skip over the lsb data, reducing the acquisition time. ? note that f_read can only be changed when fmode = 00. ? the f_read bit applies for both the output registers and the fifo. table 65. full-scale selection using active bit active bit mode 0 standby (default) 1active
mma8652fc sensors freescale semiconductor, inc. 63 6.13.2 0x2b: ctrl_reg2 system control 2 register ctrl_reg2 register is used to enable self-test, software reset, and auto-sleep. in addition, it enables you to configure the sleep and wake mode power scheme selection (oversampling modes). register quick jump table when the reset bit is enabled, all registers are reset and are loaded with default values. writing ?1? to the rst bit immediate ly resets the device, no matter whether it is in active/wake, active/sleep, or standby mode. the i 2 c communication system is reset to avoid accidental corrupted data access. at the end of the boot process the rst bit is deasserted to 0. reading this bit will return a value of zero. the (s)mods[1:0] bits select which oversampling mode is to be used, as shown in table 67 . the oversampling modes are available in both wake mode mod[1:0] and also in the sleep mode smod[1:0]. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 st rst 0 smods1 smods0 slpe mods1 mods0 figure 55. 0x2b ctrl_reg2 register (read/write) table 66. ctrl_reg2 register bit(s) field description 7s t self-test enable activates the self-test function. ? when st is set, the x, y, and z outputs will shift. 0 self-test disabled (default) 1 self-test enabled 6r s t software reset rst bit is used to activate the software reset. ? the reset mechanism is enabled in both standby and active modes. 0 device reset disabled (default) 1 device reset enabled. 4?3 smods[1:0] sleep mode power scheme selection see table 67 and table 68 00 (default) 2s l p e auto-sleep enable 0 auto-sleep is not enabled (default) 1 auto-sleep is enabled. 1?0 mods[1:0] active mode power scheme selection see table 67 and table 68 00 (default) table 67. (s)mods oversampling modes (s)mods1 (s)mods0 power mode 0 0 normal 0 1 low noise low power 1 0 high resolution 1 1 low power table 68. mods oversampling modes averaging values at each odr odr mode normal (00) low noise low power (01) high resolution (10) low power (11) current a os ratio current a os ratio current a os ratio current a os ratio 1.56 hz tbd 128 tbd 32 tbd 1024 tbd 16 50 hz tbd 4 tbd 4 tbd 32 tbd 2
mma8652fc sensors 64 freescale semiconductor, inc. note current values will be added at a later date. 100 hz tbd 4 tbd 4 tbd 16 tbd 2 200 hz tbd 4 tbd 4 tbd 8 tbd 2 400 hz tbd 4 tbd 4 tbd 4 tbd 2 800 hz tbd 2 tbd 2 tbd 2 tbd 2 table 68. mods oversampling modes averaging values at each odr (continued) odr mode normal (00) low noise low power (01) high resolution (10) low power (11) current a os ratio current a os ratio current a os ratio current a os ratio
mma8652fc sensors freescale semiconductor, inc. 65 6.13.3 0x2c: ctrl_reg3 interrupt control register ctrl_reg3 register is used to control the auto-wake/sleep function by setting the orientation or freefall/motion as an interrupt to wake. ctrl_reg3 register also configures the interrupt pins int1 and int2. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifo_gate wake_trans wake_lndprt wake_pulse wake_ff_mt 0 ipol pp_od figure 56. 0x2c ctrl_reg3 register (read/write) table 69. ctrl_reg3 register bit(s) field description 7 fifo_gate fifo gate 0 fifo gate is bypassed. (default) fifo is flushed upon the system mode transitioning from w ake to sleep m ode or from sleep to wake mode. 1 the fifo input buffer is blocked when transitioning from wake to sleep mode or from sl eep to wake mode, until the fifo is flushed. although the system transitions from wake to sleep or from sleep to wake?the contents of the fifo buffer are preserved, and new data samples are ignored until the fifo is emptied by the host application. if the fifo_gate bit is set to 1 and the fifo buffer is not emptied before the arrival of the next sample, then the fgerr bit in the sys_mod register (0x0b) will be asserted. the fgerr bit remains asserted as long as the fifo buffer remains un-emptied. emptying the fifo buffer clears the fgerr bit in the sys_mod register. 6 wake_trans wake from transient interrupt 0 transient function is bypassed in sleep mode. (default) 1 transient function interrupt can wake up system 5 wake_lndprt wake from orientation interrupt 0 orientation function is bypassed in sleep mode. (default) 1 orientation function interrupt can wake up system 4 wake_pulse wake from pulse interrupt 0 pulse function is bypassed in sleep mode. (default) 1 pulse function interrupt can wake up system 3 wake_ff_mt wake from freefall/motion interrupt 0 freefall/motion function is bypassed in sleep mode. (default) 1 freefall/motion function interrupt can wake up 1i p o l interrupt polarity selects the polarity of the interrupt signal. when ipol is 0 (default value), any interrupt event is signaled with a logical 0. 0 active low (default) 1 active high 0 pp_od push-pull/open-drain selection on interrupt pad configures the interrupt pin to push-pull or to open-drain mode. the open-drain configuration can be used for connecting multiple interrupt signals on the same interrupt line. 0 push-pull (default) 1 open drain
mma8652fc sensors 66 freescale semiconductor, inc. 6.13.4 0x2d: ctrl_reg4 interrupt enable register (read/write) ctrl_reg4 register enables the following interrupts: auto-wake/sleep, orientation detection, freefall/motion, and data ready. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 int_en_aslp int_en_fifo int_en_trans int_en_lndprt int_en_pulse int_en_ff_mt 0 int_en_drdy figure 57. 0x2d ctrl_reg4 interrupt enable register (read/write) table 70. ctrl_reg4 register bit(s) field descript i on 7 int_en_aslp auto-sleep/wake interrupt enable 0 interrupt is disabled (default) 1 interrupt is enabled note: the corresponding functional block interrupt enable bit enables the functional block to route its event detection flags to the system?s interrupt controller. the interrupt controller routes the enabled functional block interrupt to the int1 or int2 pin. 6int_en_fifo fifo interrupt enable 5int_en_trans transient interrupt enable 4 int_en_lndprt orientation (landscape/portrait) interrupt enable 3 int_en_pulse pulse detection interrupt enable 2 int_en_ff_mt freefall/motion interrupt enable 0 int_en_drdy data ready interrupt enable
mma8652fc sensors freescale semiconductor, inc. 67 6.13.5 0x2e ctrl_reg5 interrupt configuration register (read/write) ctrl_reg5 register maps the desired interrupts to int2 or int1 pins. the system?s interrupt controller (shown in figure 10 ) uses the corresponding bit field in the ctrl_reg5 register, to determine the routing table for the int1 and int2 interrupt pins. ? if the bit value is 0, then the functional block?s interrupt is routed to int2. ? if the bit value is 1, then the functional block?s interrupt is routed to int1. one or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the int_source (0x0c) register, to determine the appropriate sources of the interrupt. register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 int_cfg_aslp int_cfg_fifo int_cfg_trans int_cfg_lndprt int_cfg_pulse int_cfg_ff_mt 0 int_cfg_drdy figure 58. 0x2e: ctrl_reg5 interrupt configuration register table 71. 0x2e ctrl_reg5 register bit(s) field description 7 int_cfg_aslp auto-sleep/wake int1/int2 configuration 0 interrupt is routed to int2 pin (default) 1 interrupt is routed to int1 pin 6int_cfg_fifo fifo int1/int2 configuration 5int_cfg_trans transient int1/int2 configuration 4 int_cfg_lndprt orientation int1/int2 configuration 3int_cfg_pulse pulse int1/int2 configuration 2int_cfg_ff_mt freefall/motion int1/int2 configuration 0 int_cfg_drdy data ready int1/int2 configuration
mma8652fc sensors 68 freescale semiconductor, inc. 6.14 data calibration registers the 2?s complement offset correction registers values are used to realign the zero-g position of the x, y , and z-axis after the device is mounted on a board. the resolution of the offset registers is 1.96 mg/lsb. the 2?s complement 8-bit value would resul t in an offset compensation range 250 mg for each axis. 6.14.1 0x2f: off_x offset correction x register register quick jump table 6.14.2 0x30: off_y offset correction y register register quick jump table 6.14.3 0x31: off_z offset correction z register register quick jump table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 59. 0x2f off_x register (read/write) table 72. off_x register bit(s) field description 7?0 d[7:0] x-axis offset value 0000_0000 (default) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 60. 0x30 off_y register (read/write) table 73. off_y register bit(s) field description 7?0 d[7:0] y-axis offset value 0000_0000 (default) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 figure 61. 0x31 off_z register (read/write) table 74. off_z register bit(s) field description 7?0 d[7:0] z-axis offset value 0000_0000 (default)
mma8652fc sensors freescale semiconductor, inc. 69 7 mounting guidelines surface mount printed circuit board (pcb) layout is a critical portion of the total design. the footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the pcb and the package. with the correct footprint, the packages will self-align when subjected to a solder reflow process. these guidelines are for soldering a nd mounting the dual flat no-lead (dfn) package inertial sensors to pcbs. the purpose is to minimize the stress on the package after board mounting. the mma865xfc digital output accelerometers use the dfn package platform. this section describes suggested methods of soldering these devices to the pcb for consumer applications. 7.1 overview of soldering considerations information provided here is based on experiments executed on dfn devices. they do not represent exact conditions present at a customer site. therefore, this information should be used as guidance only and process and design optimizations are recommended to develop an application specific solution. it should be noted that with the proper pcb footprint and solder stenc il designs, the package will self-align during the solder reflow process. 7.2 halogen content this package is designed to be halogen free, exceeding most industry and customer standards. halogen free means that no homogeneous material within the assembly package shall contain chlorine (cl) in excess of 700 ppm or 0.07% weight/weight or bromine (br) in excess of 900 ppm or 0.09% weight/weight. 7.3 pcb mounting/soldering recommendations 1. the pcb land should be designed as non solder mask defined (nsmd) as shown in figure 62 . 2. no additional via pattern underneath package. 3. pcb land pad is 0.6 mm x 0.225 mm as shown in figure 62 . 4. solder mask opening = pcb land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 5. stencil opening = pcb land pad -0.05 mm smaller all around = 0.55 mm x 0.175 mm. 6. stencil thickness is 100 or 125 um. 7. do not place any components or vias at a distance less than 2 mm from the package land area. this may cause additional package stress if it is too close to the package land area. 8. signal traces connected to pads are as symmetric as possible. put dummy traces on nc pads, to have same length of exposed trace for all pads. 9. use a standard pick and place process and equipment. do not use a hand soldering process. 10. use caution when putting an assembled pcb into an enclosure, noting where the screw-down holes are and if any press-fitting is involved. it is important that the assembled pcb remain flat after assembly, to ensure optimal electronic operation of the device. 11. the pcb should be rated for the multiple lead-free reflow condition with max 260c temperature. 12. no copper traces on top layer of pcb under the package. this will cause planarity issues with board mount. freescale dfn sensors are compliant with restrictions on hazardous substances (rohs), having halide free molding compound (green) and lead-free terminations. these terminations are com patible with tin-lead (sn-pb) as well as tin-silver-copper (sn-ag-cu) solder paste soldering processes. reflow profiles applicable to those processes can be used successfully for soldering the devices.
mma8652fc sensors 70 freescale semiconductor, inc. figure 62. package mounting measurements table 75. board mounting guidelines description value (mm) landing pad width 0.225 landing pad length 0.600 solder mask pattern width 0.725 solder mask pattern length 1.950 landing pad extended length 0.200 i/o pads extended length 2.525 0.225 0.200 0.600 1.950 0.725 solder mask opening pcb landing pad 2x2 dfn package all measurements are in mm. package outline 2.525
mma8652fc sensors freescale semiconductor, inc. 71 8 tape and reel 8.1 tape dimensions figure 63. carrier tape 8.2 device orientation figure 64. device orientation on carrier tape reel carrier tape pin one orientation sprocket holes cover tape user direction of feed
mma8652fc sensors 72 freescale semiconductor, inc. 9 package dimensions figure 65. case 2162-02, issue o, 10-lead dfn?page 1
mma8652fc sensors freescale semiconductor, inc. 73 figure 66. case 2162-02, issue o, 10-lead dfn?page 2
mma8652fc sensors 74 freescale semiconductor, inc. figure 67. case 2162-02, issue o, 10-lead dfn?page 3
mma8652fc sensors freescale semiconductor, inc. 75 figure 68. case 2162-02, issue o, 10-lead dfn?page 4
mma8652fc sensors 76 freescale semiconductor, inc. 10 revision history table 76. revision history revision number revision date description of changes 0 08/2012 ? initial release
information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c- ware, energy efficient solutions logo, ki netis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. document number: mma8652fc rev. 0 08/2012

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